HV7224 Supertex, Inc., HV7224 Datasheet

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HV7224

Manufacturer Part Number
HV7224
Description
40-channel Symmetric Row Driver
Manufacturer
Supertex, Inc.
Datasheet

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Features
Functional Block Diagram
HVCMOS
Symmetric row drive (reduces latent imaging in
ACTFEL displays)
Output voltage up to +240V
Low power level shifting
Source/sink current minimum 70mA
Shift register speed 3MHz
Pin-programmable shift direction (DIR, SHIFT)
®
technology
Polarity
SHIFT
DIOA
DIOB
VDD
VPP
CLK
DIR
OE
40-Channel Symmetric Row Driver
GND
S/R
General Description
The HV72 is a low-voltage serial to high-voltage parallel converters
with push-pull outputs. It is especially suitable for use as a
symmetric row driver in AC thin-fi lm electroluminescent (ACTFEL)
displays.
When the data reset pin (DRIO) is at logic high, it will reset all the
outputs of the internal shift register to zero. At the same time, the
output of the shift register will start shifting a logic high from the
least signifi cant bit to the most signifi cant bit. The DRIO can
be triggered at any time. The DIR and SHIFT pins control the
direction of data shift through the device. When DIR is at logic
high, DRIOA is the input and DRIOB is the output. When DIR is
grounded, DRIOB is the input and the DRIOA is the output. See
the Output Sequence Operation Table for output sequence. The
POL and OE pins perform the polarity select and output enable
function respectively. Data is loaded on the low to high transition
of the clock. A logic high will cause the output to swing to VPP if
POL is high, or to GND if POL is low. All outputs will be in High-Z
state if OE is at logic high. Data output buffers are provided for
cascading devices.
LT = Level Translator
LT
LT
LT
N
P
HVOUT1
HVOUT40
HVOUT2
HV7224

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HV7224 Summary of contents

Page 1

... A logic high will cause the output to swing to VPP if POL is high GND if POL is low. All outputs will be in High-Z state logic high. Data output buffers are provided for cascading devices. S Level Translator HV7224 P LT HVOUT1 N LT HVOUT2 ...

Page 2

... YY = Year Sealed YYWW WW = Week Sealed HV7224FG LLLLLLLLL L = Lot Number C = Country of Origin* Bottom Marking A = Assembler ID* = “Green” Packaging CCCCCCCC AAA *May be part of top marking 64-Lead PQFP (PG) Min Max 4.5 5.5 0 240 0 0. 3.0 -40 +85 - ±70 - ±300 HV7224 Units MHz ° ...

Page 3

... L L 2.0 µ 330pF // R = 10kΩ 600 330pF // R = 10kΩ 250 15pF L 250 15pF L 2.0 µ 330pF // R = 10kΩ 2.0 µ 330pF // R = 10kΩ µs --- - µs --- One active output driving 45 V/µs 4.7nF load HV7224 DD ...

Page 4

... SUC ONF t POW 50% 50% t OEW 50 SUE ONR 90% 10% 90% 10 SUE ONF 4 HV7224 VPP HVOUT GND (Power) High Voltage Outputs VIH 50% 50% VIL VIH VIL t DHL VOH 50% VOL t HC 90% VOH High Impedance 10% VOL t HC VIH VIL VIH ...

Page 5

... Data Reset In Data Reset Out IOB IOA IOA IOB IOB IOA IOA IOB 5 HV7224 HV Outputs HIGH All O/P HIGH Sequence Direction OUT 40 → → → 1 → 40 → → 40 → 1 → 20 ...

Page 6

... GND (Power GND (Logic DIR 41 26 VDD 42 27 CLK SHIFT DRIOA HV7224 Function Pin # Function N/C 49 HVOUT25/16 DRIOB 50 HVOUT26/ HVOUT27/14 N/C 52 HVOUT28/13 POL 53 HVOUT29/12 N/C 54 HVOUT30/11 VDD 55 HVOUT31/10 N/C 56 HVOUT32/9 GND (Logic) 57 HVOUT33/8 GND (Power) ...

Page 7

... Modifi ed Version of JEDEC Registration MO-112, Variation CB-1, Issue B, Sept.95. Drawings not to scale. (The package drawing(s) in this data sheet may not refl ect the most current specifi cations. For the latest package outline information go to http://www.supertex.com/packaging.html.) Doc.# DSFP-HV7224 A083107 D D1 ...

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