WM8768 Wolfson Microelectronics plc, WM8768 Datasheet - Page 8

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WM8768

Manufacturer Part Number
WM8768
Description
24-bit, 192khz 8-channel Dac
Manufacturer
Wolfson Microelectronics plc
Datasheet

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WM8768
MASTER CLOCK TIMING
Figure 1 DAC Master Clock Timing Requirements
Table 1 Master Clock Timing Requirements
Note:
If MCLK period is longer than maximum specified above, power-saving mode is entered and DACs are powered down with
internal digital audio filters being reset. In this power-saving mode, all registers will retain their values and can be
accessed in the normal manner through the control interface. Once MCLK is restored, the DACs are automatically
powered up, but a write to the volume update register bit is required to restore the correct volume settings.
DIGITAL AUDIO INTERFACE – MASTER MODE
Figure 2 Audio Interface - Master Mode
w
Test Conditions
AVDD, VREFP = 5V, DVDD = 3.3V, AGND, VREFN = 0V, DGND = 0V, T
otherwise stated.
PARAMETER
System Clock Timing Information
MCLK System clock pulse width
high
MCLK System clock pulse width
low
MCLK System clock cycle time
MCLK Duty cycle
Power-saving mode activated
Normal mode resumed
WM8768
MCLK
DAC
DIN1/2/3/4
LRCLK
BCLK
4
SYMBOL
t
t
t
MCLKH
MCLKL
MCLKY
t
MCLKL
t
MCLKY
DECODER
After MCLK re-started
After MCLK stopped
TEST CONDITIONS
t
DSP/
MCLKH
A
= +25
o
C, fs = 48kHz, MCLK = 256fs unless
40:60
MIN
0.5
11
11
28
2
TYP
PD Rev 4.2 July 2005
60:40
1000
MAX
10
1
Production Data
MCLK
cycle
UNIT
Us
ns
ns
ns
8

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