PIC16C765 Microchip Technology Inc., PIC16C765 Datasheet
PIC16C765
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PIC16C765 Summary of contents
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... Compare is 16-bit, max. resolution is 167 ns - PWM maximum resolution is 10-bit • 8-bit multi-channel Analog-to-Digital converter • Universal Synchronous Asynchronous Receiver Transmitter (USART/SCI) • Parallel Slave Port (PSP) 8-bits wide, with exter- nal RD, WR and CS controls (PIC16C765 only) Preliminary RB7 • ...
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... NC 32 RC0/T1OSO/T1CKI 31 OSC2/CLKOUT 30 OSC1/CLKIN RE2/CS/AN7 26 RE1/WR/AN6 25 RE0/RD/AN5 24 RA5/AN4 23 RA4/T0CKI PIC16C765 6 MHz or 24 MHz POR, BOR (PWRT, OST) 8K 256 (Ports channel x 8 bit Yes USB, USART/SCI Yes 2000 Microchip Technology Inc. ...
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... However, we realize that we may have missed a few things. If you find any information that is missing or appears in error, please: • Fill out and mail in the reader response form in the back of this data sheet. • E-mail us at webmaster@microchip.com. We appreciate your assistance in making this a better document. 2000 Microchip Technology Inc. PIC16C745/765 To Our Valued Customers Preliminary DS41124C-page 3 ...
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... PIC16C745/765 NOTES: DS41124C-page 4 Preliminary 2000 Microchip Technology Inc. ...
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... The PIC16C745 device has 22 I/O pins. The PIC16C765 device has 33 I/O pins. Each device has 256 bytes of RAM. In addition, several peripheral fea- tures are available including: three timer/counters, two Capture/Compare/PWM modules and two serial ports. ...
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... PIC16C745/765 NOTES: DS41124C-page 6 Preliminary 2000 Microchip Technology Inc. ...
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... The OTP devices, packaged in plastic packages, per- mit the user to program them once. In addition to the program memory, the configuration bits must also be programmed. 2000 Microchip Technology Inc. PIC16C745/765 2.3 Quick-Turnaround-Production (QTP) Devices Microchip offers a QTP Programming Service for fac- tory production orders ...
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... PIC16C745/765 NOTES: DS41124C-page 8 Preliminary 2000 Microchip Technology Inc. ...
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... Data Resolution x14 x8 PIC16C745 8K 256 28 PIC16C765 8K 256 40 The PIC16C745/765 can directly or indirectly address its register files or data memory. All special function registers, including the program counter, are mapped in the data memory. The PIC16C745/765 has an orthog- onal (symmetrical) instruction set that makes it possible to carry out any operation on any register using any addressing mode ...
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... Dual Port RAM USB USART Preliminary PORTA RA0/AN0 RA1/AN1 RA2/AN2 RA3/AN3/V REF RA4/T0CKI RA5/AN4 PORTB RB0/INT RB<7:1> PORTC RC0/T1OSO/T1CKI RC1/T1OSI/CCP2 RC2/CCP1 RC6/TX/CK RC7/RX/DT PORTD (2) RD3:0/PSP3:0 (2) RD4/PSP4 (2) RD5/PSP5 (2) RD6/PSP6 (2) RD7/PSP7 PORTE (2) RE0/AN5/RD (2) RE1/AN6/WR (2) RE2/AN7/CS V USB XCVR D- D+ 2000 Microchip Technology Inc. ...
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... RC2/CCP1 CCP1 V V USB USB Legend open drain Schmitt Trigger Note 1: Weak pull-ups. PORT B pull-ups are byte wide programmable. 2: PIC16C765 only. 2000 Microchip Technology Inc. PIC16C745/765 Input Output Type Type ST — Master Clear Power — Programming Voltage Xtal — ...
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... RE2/CS/AN7 CS AN7 Legend open drain Schmitt Trigger Note 1: Weak pull-ups. PORT B pull-ups are byte wide programmable. 2: PIC16C765 only. DS41124C-page 12 Input Output Type Type ST CMOS Bi-directional I/O — CMOS USART Async Transmit ST CMOS USART Master Out/Slave In Clock ST CMOS ...
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... Instruction @ address SUB_1 Note: All instructions are single cycle, except for any program branches. These take two cycles, since the fetch instruction is “flushed” from the pipeline, while the new instruction is being fetched and then executed. 2000 Microchip Technology Inc. PIC16C745/765 3.2 Instruction Flow/Pipelining An “ ...
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... PIC16C745/765 NOTES: DS41124C-page 14 Preliminary 2000 Microchip Technology Inc. ...
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... Page 0 Page 1 On-chip Program Memory Page 2 Page 3 2000 Microchip Technology Inc. PIC16C745/765 4.2 Data Memory Organization The data memory is partitioned into multiple banks which contain the General Purpose Registers (GPR) and the Special Function Registers (SFR). Bits RP1 and RP0 are the bank select bits. ...
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... Microchip Technology Inc. ...
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... These registers can be addressed from any bank. 4: The Parallel Slave Port (PORTD and PORTE) is not implemented on the PIC16C745, always maintain these bits clear. 2000 Microchip Technology Inc. The Special Function Registers can be classified into two sets (core and peripheral). Those registers associ- ated with the “ ...
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... TRMT TX9D 0000 -010 0000 -010 0000 0000 0000 0000 — — — — — — — — — — PCFG1 PCFG0 ---- -000 ---- -000 2000 Microchip Technology Inc. ...
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... Other (non power-up) RESETS include external RESET through MCLR and Watchdog Timer Reset. 3: These registers can be addressed from any bank. 4: The Parallel Slave Port (PORTD and PORTE) is not implemented on the PIC16C745, always maintain these bits clear. 2000 Microchip Technology Inc. PIC16C745/765 Bit 5 ...
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... USB_RST --00 0000 --00 0000 CRC5 PID_ERR 0000 0000 0000 0000 CRC5 PID_ERR 0000 0000 0000 0000 — — ---x xx-- ---u uu-- SUSPND — --x0 000- --xq qqq- ADDR1 ADDR0 -000 0000 -000 0000 SWSTAT1 SWSTAT0 0000 0000 0000 0000 0000 0000 0000 0000 2000 Microchip Technology Inc. ...
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... Legend unknown unchanged value depends on condition unimplemented read as ’0’. Shaded locations are unimplemented, read as ‘0’. Note 1: Other (non power-up) RESETS include external RESET through MCLR and Watchdog Timer Reset. 2000 Microchip Technology Inc. PIC16C745/765 Bit 5 Bit 4 Bit 3 Bit 2 ...
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... Note 1: The C and DC bits operate as borrow and digit borrow bits, respectively, in subtrac- tion. See the SUBLW and SUBWF instruc- tions for examples. R-1 R/W-x R/W-x R/W-x ( bit0 (1) (1) Preliminary R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ Value at POR reset 2000 Microchip Technology Inc. ...
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... Microchip Technology Inc. Note: To achieve a 1:1 prescaler assignment for the TMR0 register, assign the prescaler to the Watchdog Timer. R/W-1 R/W-1 R/W-1 R/W-1 PSA PS2 PS1 PS0 ...
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... GIE (INTCON<7>). User soft- ware should ensure the appropriate inter- rupt flag bits are clear prior to enabling an interrupt R/W-0 R/W-0 R/W-0 R/W-x RBIE T0IF INTF RBIF bit0 Preliminary . R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ Value at POR reset 2000 Microchip Technology Inc. ...
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... TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt Note 1: Parallel slave ports not implemented on the PIC16C745; always maintain this bit clear. 2000 Microchip Technology Inc. PIC16C745/765 Note: Bit PEIE (INTCON<6>) must be set to enable any peripheral interrupt. ...
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... GIE (INTCON<7>). User soft- ware should ensure the appropriate inter- rupt flag bits are clear prior to enabling an interrupt. R/W-0 R/W-0 R/W-0 R/W-0 USBIF CCP1IF TMR2IF TMR1IF bit0 Preliminary R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ Value at POR reset 2000 Microchip Technology Inc. ...
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... Capture Mode TMR1 register capture occurred (must be cleared in software TMR1 register capture occurred Compare Mode TMR1 register compare match occurred (must be cleared in software TMR1 register compare match occurred PWM Mode Unused 2000 Microchip Technology Inc. PIC16C745/765 U-0 U-0 U-0 R/W-0 — — ...
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... Note: BOR is unknown on POR. It must be set by the user and checked on subsequent RESETS to see if BOR is clear, indicating a brown-out has occurred. U-0 U-0 R/W-0 R/W-q — — POR BOR bit0 Preliminary R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ Value at POR reset 2000 Microchip Technology Inc. ...
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... PUSHed eight times, the ninth push overwrites the value that was stored from the first push. The tenth push overwrites the second push (and so on). 2000 Microchip Technology Inc. PIC16C745/765 Note 1: There are no status bits to indicate stack overflow or stack underflow conditions. ...
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... FFh 17Fh 1FFh Bank 1 Bank 2 Bank 3 Preliminary INDIRECT ADDRESSING 0x20 ;initialize pointer FSR ;to RAM INDF ;clear INDF register FSR,F ;inc pointer FSR,4 ;all done? NEXT ;no clear next ;yes continue Indirect Addressing 7 0 FSR register location select 2000 Microchip Technology Inc. ...
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... Configure all pins MOVWF ADCON1 ; as digital inputs MOVLW 0xCF ; Value used to ; initialize data ; direction MOVWF TRISA ; Set RA<3:0> as inputs ; RA<5:4> as outputs ; TRISA<7:6> are always ; read as ’0’. 2000 Microchip Technology Inc. PIC16C745/765 FIGURE 5-1: BLOCK DIAGRAM OF RA<3:0> AND RA5 PINS Data Bus Port Q CK Data Latch D ...
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... Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 RA5 RA4 RA3 RA2 RA1 PORTA Data Direction Register — — — PCFG2 PCFG1 PCFG0 Preliminary Description Value on: Value on all Bit 0 POR, other resets BOR RA0 --0x 0000 --0u 0000 --11 1111 --11 1111 ---- -000 ---- -000 2000 Microchip Technology Inc. ...
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... Any read or write of PORTB. This will end the mismatch condition. b) Clear flag bit RBIF. 2000 Microchip Technology Inc. PIC16C745/765 A mismatch condition will continue to set flag bit RBIF. Reading PORTB will end the mismatch condition, and allow flag bit RBIF to be cleared. ...
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... Bit 2 Bit 1 RB6 RB5 RB4 RB3 RB2 RB1 T0CS T0SE PSA PS2 PS1 Preliminary Description Value on: Value on all Bit 0 POR, other resets BOR RB0 uuuu uuuu xxxx xxxx 1111 1111 1111 1111 PS0 1111 1111 1111 1111 2000 Microchip Technology Inc. ...
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... BCF, XORWF) with TRISC as destination should be avoided. The user should refer to the corresponding peripheral section for the correct TRIS bit settings. 2000 Microchip Technology Inc. PIC16C745/765 FIGURE 5-5: PORTC BLOCK DIAGRAM (1) Port/Peripheral Select ...
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... USART Async Receive ST CMOS USART Data I/O Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 — — — RC2 RC1 — — — TRISC2 TRISC1 TRISC0 11-- -111 Preliminary Description Value on: Value on all Bit 0 POR, other resets BOR RC0 xx-- -xxx uu-- -uuu 11-- -111 2000 Microchip Technology Inc. ...
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... Bit 6 08h RD7 RD6 (1) PORTD 88h (1) PORTD Data Direction Register TRISD Legend unknown unchanged unimplemented read as '0'. Shaded cells are not used by PORTD. Note 1: PIC16C765 only. 2000 Microchip Technology Inc. PIC16C745/765 FIGURE 5-6: PORTD BLOCK DIAGRAM Data Bus D WR Port CK Data Latch ...
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... Register 5-1 shows the TRISE register, which also con- trols the parallel slave port operation. PORTE pins may be multiplexed with analog inputs (PIC16C765 only). The operation of these pins is selected by control bits in the ADCON1 register. When selected as an analog input, these pins will read as ’0’s. ...
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... PORTE 89h (1) IBF OBF IBOV TRISE 9Fh ADCON1 — — Legend unknown unchanged unimplemented read as '0'. Shaded cells are not used by PORTE. Note 1: PIC16C765 only. 2000 Microchip Technology Inc. PIC16C745/765 (1) U-0 R/W-1 R/W-1 R/W-1 — TRISE2 TRISE1 TRISE0 Bit 4 Bit 3 Bit 2 Bit 1 — ...
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... FIGURE 5-8: PORTD AND PORTE BLOCK DIAGRAM (PARALLEL SLAVE PORT) Data Bus D WR Port PCFG<2:0> Port One bit of PORTD Set interrupt flag PSPIF (PIR1<7>) Preliminary RDx pin TTL Read TTL RD Chip Select TTL CS Write TTL WR 2000 Microchip Technology Inc. ...
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... INTCON GIE PEIE Legend unknown unchanged unimplemented read as '0'. Shaded cells are not used by the Parallel Slave Port. Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C745. Always maintain these bits clear. 2: PIC16C765 only. 2000 Microchip Technology Inc ...
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... PIC16C745/765 NOTES: DS41124C-page 42 Preliminary 2000 Microchip Technology Inc. ...
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... X Watchdog Timer PSA WDT Enable bit Note: T0CS, T0SE, PSA, PS<2:0> are (OPTION_REG<5:0>). 2000 Microchip Technology Inc. PIC16C745/765 Counter mode is selected by setting bit T0CS (OPTION_REG<5>). In counter mode, Timer0 will increment either on every rising or falling edge of pin RA4/T0CKI. The incrementing edge is determined by the Timer0 (OPTION_REG< ...
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... Bit 4 Bit 3 Bit 2 Bit 1 T0IE INTE RBIE T0IF INTF T0CS T0SE PSA PS2 PS1 Preliminary Value on: Value on all Bit 0 POR, other resets BOR xxxx xxxx uuuu uuuu RBIF 0000 000x 0000 000u PS0 1111 1111 1111 1111 2000 Microchip Technology Inc. ...
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... TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 Note 1: On the rising edge after the first falling edge. 2000 Microchip Technology Inc. PIC16C745/765 In timer mode, Timer1 increments every instruction cycle. In counter mode, it increments on every rising edge of the external clock input. Timer1 can be enabled/disabled by setting/clearing control bit TMR1ON (T1CON< ...
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... The pres- caler however will continue to increment. 0 TMR1L 1 TMR1ON on/off T1SYNC 1 Prescaler T1OSCEN F INT Enable Internal 0 (1) Oscillator Clock 2 T1CKPS<1:0> TMR1CS Preliminary Synchronized clock input Synchronize det SLEEP input 2000 Microchip Technology Inc. ...
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... It will continue to run during SLEEP primarily intended for use with a 32 kHz crystal. Table 7-1 shows the capacitor selection for the Timer1 oscillator. 2000 Microchip Technology Inc. PIC16C745/765 TABLE 7-1: CAPACITOR SELECTION FOR ...
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... USBIE CCP1IE TMR2IE Preliminary Value on: Value on Bit 1 Bit 0 POR, all other BOR resets INTF RBIF 0000 000x 0000 000u TMR1IF 0000 0000 0000 0000 TMR1IE 0000 0000 0000 0000 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu 2000 Microchip Technology Inc. ...
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... Timer2 is off bit 1-0: T2CKPS<1:0>: Timer2 Clock Prescale Select bits 00 = Prescaler Prescaler Prescaler is 16 2000 Microchip Technology Inc. PIC16C745/765 8.1 Timer2 Prescaler and Postscaler The prescaler and postscaler counters are cleared when any of the following occurs: • a write to the TMR2 register • ...
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... RCIE TXIE USBIE CCP1IE TMR2IE Preliminary Value on: Value on Bit 0 POR, all other BOR resets 0000 000x 0000 000u RBIF 0000 0000 0000 0000 TMR1IF 0000 0000 0000 0000 TMR1IE 0000 0000 0000 0000 1111 1111 1111 1111 2000 Microchip Technology Inc. ...
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... The PWMs will have the same frequency and update rate (TMR2 interrupt). PWM Capture None. PWM Compare None. 2000 Microchip Technology Inc. PIC16C745/765 CCP2 Module: Capture/Compare/PWM Register1 (CCPR2) is com- prised of two 8-bit registers: CCPR2L (low byte) and CCPR2H (high byte). The CCP2CON register controls the operation of CCP2. The special event trigger is ...
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... Compare mode, generate software interrupt on match (CCPnIF bit is set, CCPn pin is unaffected) 1011 = Compare mode, trigger special event (CCPnIF bit is set; CCPn resets TMR1or TMR3) 11xx = PWM mode DS41124C-page 52 R/W-0 R/W-0 R/W-0 R/W-0 CCPnM2 CCPnM1 CCPnM0 Preliminary R = Readable bit W = Writable bit bit0 U = Unimplemented bit, read as ‘0’ Value at POR reset 2000 Microchip Technology Inc. ...
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... Capture and Enable edge detect TMR1H CCP1CON<3:0> Q’s 2000 Microchip Technology Inc. PIC16C745/765 9.1.2 TIMER1 MODE SELECTION Timer1 must be running in timer mode or synchronized counter mode for the CCP module to use the capture feature. In asynchronous counter mode, the capture operation may not work. ...
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... A PWM output (Figure 9-4) has a time base (period) and a time that the output stays high (duty cycle). The fre- quency of the PWM is the inverse of the period (1/period). Preliminary the SIMPLIFIED PWM BLOCK DIAGRAM CCP1CON<5:4> RC2/CCP1 (Note 1) S TRISC <2> Clear Timer, CCP1 pin and latch D.C. 2000 Microchip Technology Inc. ...
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... The CCPR1H register and a 2-bit internal latch are used to double buffer the PWM duty cycle. This double buffering is essential for glitchless PWM operation. 2000 Microchip Technology Inc. PIC16C745/765 When the CCPR1H and 2-bit latch match TMR2 con- catenated with an internal 2-bit Q clock or 2 bits of the TMR2 prescaler, the CCP1 pin is cleared ...
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... CCP2IF ---- ---0 ---- ---0 TMR1IE 0000 0000 0000 0000 — CCP2IE ---- ---0 ---- ---0 1111 1111 1111 1111 0000 0000 0000 0000 1111 1111 1111 1111 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu 2000 Microchip Technology Inc. ...
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... USB peri- odically polls these devices at a fixed rate to see if there is data to transfer. - Control Transfers are used for configuration purposes. 2000 Microchip Technology Inc. PIC16C745/765 10.1.2 FRAMES Information communicated on the bus is grouped in a format called Frames. Each Frame duration and is composed of multiple transfers ...
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... USB protocol. A simple Put/Get interface is imple- mented to allow most of the USB processing to take place in the background within the USB interrupt ser- vice routine. Applications are encouraged to use the provided libraries during both enumeration and config- ured operation. Preliminary 2000 Microchip Technology Inc. ...
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... FIGURE 10-1: USB TOKENS USB RESET USB_RST Interrupt Generated SETUP TOKEN IN TOKEN OUT TOKEN = Host = Device 2000 Microchip Technology Inc. PIC16C745/765 DATA ACK DATA ACK DATA ACK Preliminary TOK_DNE Interrupt Generated TOK_DNE Interrupt Generated TOK_DNE Interrupt Generated DS41124C-page 59 ...
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... PIR1 (USBIF). Once an interrupt bit has been set, it must be cleared by writing a zero. R/C-0 R/C-0 R/C-0 R/C-0 UERR USB_RST Preliminary R = Readable bit C = Clearable bit bit0 U = Unimplemented bit, read as ‘0’ Value at POR reset 2000 Microchip Technology Inc. ...
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... UERR: Set to enable ERROR interrupts 1 = ERROR interrupt enabled 0 = ERROR interrupt disabled bit 0: USB_RST: Set to enable USB_RST interrupts 1 = USB_RST interrupt enabled 0 = USB_RST interrupt disabled Note 1: This interrupt is the only interrupt active during UCTRL.SUSPEND = 1. 2000 Microchip Technology Inc. PIC16C745/765 R/W-0 R/W-0 R/W-0 R/W-0 TOK_DNE ACTIVITY UERR USB_RST ...
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... Thus, the interrupt will typically not correspond with the end of a token being processed. R/C-0 R/C-0 R/C-0 R/C-0 DFN8 CRC16 CRC5 PID_ERR Preliminary R/C Readable bit C = Clearable bit bit0 U = Unimplemented bit, read as ‘0’ Value at POR reset 2000 Microchip Technology Inc. ...
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... CRC16 interrupt enabled 0 = CRC16 interrupt disabled bit 1: CRC5: Set this bit to enable CRC5 interrupts 1 = CRC5 interrupt enabled 0 = CRC5 interrupt disabled bit 0: PID_ERR: Set this bit to enable PID_ERR interrupts 1 = PID_ERR interrupt enabled 0 = PID_ERR interrupt disabled 2000 Microchip Technology Inc. PIC16C745/765 R/W-0 R/W-0 R/W-0 R/W-0 DFN8 CRC16 CRC5 PID_ERR ...
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... STAT value. If the data in the STAT holding register is valid, the SIE will immediately reassert the TOK_DNE interrupt. R-X R-X R-X U-0 ENDP1 ENDP0 IN — Preliminary U-0 — Readable bit W = Writable bit bit0 U = Unimplemented bit, read as ‘0’ Value at POR reset X = Don’t care 2000 Microchip Technology Inc. ...
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... V regulation will be different between suspend and non-suspend modes. The V USB driven, however the transceiver outputs are disabled USB module in power conserve mode 0 = USB module normal operation bit 0: Unimplemented: Read as ’0’ 2000 Microchip Technology Inc. PIC16C745/765 R/W-0 R/W-0 R/W-0 U-0 — bit0 pin will be driven with 3.3V (nominal) ...
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... Note 1: Application should not modify these bits. DS41124C-page 66 R/W-0 R/W-0 R/W-0 R/W-0 ADDR3 ADDR2 ADDR1 ADDR0 bit0 R/W-0 R/W-0 R/W-0 R/W Enumeration Status Preliminary R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ Value at POR reset R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ Value at POR reset 2000 Microchip Technology Inc. ...
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... USB to return a STALL handshake. The EP_STALL bit can be set or cleared by the SIE. Refer to the USB 1.1 Specification, Sections 4.4.4 and 8.5.2 for more details on the STALL protocol. 2000 Microchip Technology Inc. PIC16C745/765 10.5.1.10 USB Endpoint Control Register (EPCn) The Endpoint Control Register contains the endpoint ...
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... Warning: The bit entries should be written as a whole word instead of using BSF, BCF to affect individual bits. This is because of the dual meaning of the bits. Bit sets and clears may leave other bits set incor- rectly and present incorrect data to the SIE. Preliminary 2000 Microchip Technology Inc. ...
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... BD in this location. The BD is not consumed by the SIE (the own bit remains and the rest of the BD are unchanged) when a BSTALL bit is set. bit 1-0: Reserved: Read as ’X’ Note: Recommend that users not use BSF, BCF due to the dual functionality of this register. 2000 Microchip Technology Inc. PIC16C745/765 W-X W-X U-X ...
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... R/W-X R/W-X R/W-X R/W-X BC3 BC2 BC1 BC0 bit0 Preliminary R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ Value at POR reset X = Don’t care R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ Value at POR reset X = Don’t care 2000 Microchip Technology Inc. ...
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... USB 1.1 Specification. A +20% 200nF capacitor is required on V for regulator stability. USB TABLE 10-1: USB PORT FUNCTIONS Name Function V V USB USB Legend open drain Schmitt Trigger 2000 Microchip Technology Inc. PIC16C745/765 R/W-X R/W-X R/W-X R/W-X BA3 BA2 BA1 BA0 bit0 FIGURE 10-2: EXTERNAL CIRCUITRY APPLICATION PIC16C745/765 V USB D- D+ Note: The PIC16C745/765 requires an external resistor and capacitor to communicate with a host over USB ...
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... With devices that don’t support common RAM, the W register must be provided for in each bank. The 16C745/765 can save the appropriate registers in Common RAM and not have to waste a byte in each bank for W register. Preliminary ® MCU is only 8 2000 Microchip Technology Inc. ...
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... An application might call DeInitUSB if it was finished communicating to the host and didn't want to be polled any more. 2000 Microchip Technology Inc. PIC16C745/765 PutUSB (Buffer pointer, Buffer size, Endpoint) sends data up to the host. The pointer to the block of data to transmit is in the FSR/IRP, and the block size and end- point is passed in W register ...
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... PICmicro device to SLEEP, if the USB peripheral has detected no activity on the bus. This powers down most of the device to minimal current draw. This call should be made at a point in the main loop where all other processing is complete. Preliminary interrupt, transitions to 2000 Microchip Technology Inc. ...
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... USB_MAIN.ASM - Sample interrupt service routine. • HIDCLASS.ASM - Handles the HID class specific commands. 2000 Microchip Technology Inc. PIC16C745/765 enumeration is complete, and then polls EP1 OUT to see if there is any data available. When a buffer is available copied to the IN buffer. Presumably your application would do something more interesting with the data than this example ...
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... PIC16C745/765 NOTES: DS41124C-page 76 Preliminary 2000 Microchip Technology Inc. ...
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... TRMT: Transmit Shift Register Status bit 1 = TSR empty 0 = TSR full bit 0: TX9D: 9th bit of transmit data. (Can be used for parity.) 2000 Microchip Technology Inc. PIC16C745/765 as a half duplex synchronous system that can commu- nicate with peripheral devices, such as A/D or D/A inte- grated circuits, Serial EEPROMs, etc. ...
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... Overrun error (Can be cleared by clearing bit CREN overrun error bit 0: RX9D: 9th bit of received data. (Can be used for parity.) DS41124C-page 78 U-0 R-0 R-0 R-x — FERR OERR RX9D bit0 Preliminary R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ Value at POR reset 2000 Microchip Technology Inc. ...
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... Microchip Technology Inc. PIC16C745/765 It may be advantageous to use the high baud rate (BRGH = 1) even for slower baud clocks. This is because the F /(16(X + 1)) equation can reduce the INT baud rate error in some cases. Writing a new value to the SPBRG register causes the BRG timer to be reset (or cleared) ...
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... Bit 4 Bit 3 Bit 2 Bit 1 TXEN SYNC — BRGH TRMT TX9D SREN CREN — FERR OERR RX9D Preliminary Value on: Value on all Bit 0 POR, other resets BOR 0000 -010 0000 -010 0000 -00x 0000 -00x 0000 0000 0000 0000 2000 Microchip Technology Inc. ...
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... Interrupt TXEN Baud Rate CLK SPBRG Baud Rate Generator 2000 Microchip Technology Inc. PIC16C745/765 ( PIE1<4>). Flag bit TXIF will be set regardless of the state of enable bit TXIE and cannot be cleared in soft- ware. It will reset only when new data is loaded into the TXREG register. While flag bit TXIF indicated the sta- tus of the TXREG register, another bit TRMT (TXSTA< ...
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... Transmit Shift Reg. Value on: Value on Bit 0 POR, all other BOR Resets TMR1IF 0000 0000 0000 0000 RX9D 0000 -00x 0000 -00x 0000 0000 0000 0000 TMR1IE 0000 0000 0000 0000 TX9D 0000 -010 0000 -010 0000 0000 0000 0000 2000 Microchip Technology Inc. ...
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... CREN Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word, causing the OERR (overrun) bit to be set. 2000 Microchip Technology Inc. PIC16C745/765 possible for two bytes of data to be received and trans- ferred to the RCREG FIFO and a third byte to begin shifting to the RSR register ...
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... Preliminary Value on: Value on Bit 0 POR, all other BOR Resets TMR1IF 0000 0000 0000 0000 RX9D 0000 -00x 0000 -00x 0000 0000 0000 0000 TMR1IE 0000 0000 0000 0000 TX9D 0000 -010 0000 -010 0000 0000 0000 0000 2000 Microchip Technology Inc. ...
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... TSR register is empty transfer to the TXREG register will result in an immediate transfer to TSR resulting in an empty TXREG. Back-to-back transfers are possible. 2000 Microchip Technology Inc. PIC16C745/765 Clearing enable bit TXEN, during a transmission, will cause the transmission to be aborted and will reset the transmitter ...
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... Resets BOR TMR1IF 0000 0000 0000 0000 RX9D 0000 -00x 0000 -00x 0000 0000 0000 0000 TMR1IE 0000 0000 0000 0000 TX9D 0000 -010 0000 -010 0000 0000 0000 0000 bit 1 bit 7 WORD 2 ’1’ bit6 bit7 2000 Microchip Technology Inc. ...
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... Legend unknown unimplemented read as '0'. Shaded cells are not used for synchronous master reception. Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C745; always maintain these bits clear. 2000 Microchip Technology Inc essential to clear bit OERR set. The ninth receive bit is buffered the same way as the receive data ...
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... Note: Timing diagram demonstrates Sync Master mode with bit SREN = ’1’ and bit BRG = ’0’. DS41124C-page Q4Q1 Q4Q1 Q4Q1 bit1 bit2 bit3 bit4 bit5 Preliminary bit6 bit7 ’0’ 2000 Microchip Technology Inc. ...
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... If 9-bit transmission is selected, the ninth bit should be loaded in bit TX9D. 7. Start transmission by loading data to the TXREG register. 2000 Microchip Technology Inc. PIC16C745/765 11.4.2 USART SYNCHRONOUS SLAVE RECEPTION The operation of the Synchronous Master and Slave modes is identical, except in the case of the SLEEP mode. Also, bit SREN is a don’ ...
Page 90
... Value on: Value on all Bit 0 POR, other Resets BOR TMR1IF 0000 0000 0000 0000 RX9D 0000 -00x 0000 -00x 0000 0000 0000 0000 TMR1IE 0000 0000 0000 0000 TX9D 0000 -010 0000 -010 0000 0000 0000 0000 2000 Microchip Technology Inc. ...
Page 91
... CONVERTER (A/D) MODULE The 8-bit Analog-To-Digital (A/D) converter module has five inputs for the PIC16C745 and eight for the PIC16C765. The A/D allows conversion of an analog input signal to a corresponding 8-bit digital value. The output of the sample and hold is the input into the converter, which generates the result via successive approximation ...
Page 92
... A/D conversion not in progress (This bit is automatically cleared by hardware when the A/D conversion is complete) bit 1: Unimplemented: Read as '0' bit 0: ADON: A/D On bit 1 = A/D converter module is operating 0 = A/D converter module is shutoff and consumes no operating current Note 1: A/D channels 5, 6 and 7 are implemented on the PIC16C765 only. 2: Choose F / maintain 8-bit A/D accuracy at 24 MHz. INT RC DS41124C-page 92 R/W-0 ...
Page 93
... A 001 010 011 100 101 11x A = Analog input D = Digital I/O Note 1: A/D channels 5, 6 and 7 are implemented on the PIC16C765 only. 2000 Microchip Technology Inc. PIC16C745/765 U-0 R/W-0 R/W-0 R/W-0 — PCFG2 PCFG1 PCFG0 AN4 AN3 AN2 AN1 AN0 ...
Page 94
... CHS<2:0> (Input voltage 000 or 010 or 100 or 11x 001 or 011 or 101 PCFG<2:0> Preliminary . A minimum wait 111 RE2/AN7(1) 110 RE1/AN6(1) 101 RE0/AN5(1) 100 RA5/AN4 011 RA3/AN3/V REF 010 RA2/AN2 001 RA1/AN1 000 RA0/AN0 2000 Microchip Technology Inc. ...
Page 95
... (Temp -25 C)(0. COFF 2000 Microchip Technology Inc. The maximum recommended impedance for ana- log sources After the analog input channel is selected (changed), the acquisition must pass before the conversion can be started. To calculate Equation 12-1 may be used. This equation assumes that 1/2 LSb error is used (512 steps for the A/D) ...
Page 96
... A device RESET forces all registers to their RESET state. The A/D module is disabled and any conversion in progress is aborted. All pins with analog functions are configured as available inputs. The ADRES register will contain unknown data after a Power-on Reset. Preliminary wait AD 2000 Microchip Technology Inc. ...
Page 97
... OBF Legend unknown unchanged unimplemented read as '0'. Shaded cells are not used for A/D conversion. Note 1: These bits are reserved on the PIC6C745; always maintain these bits clear. 2000 Microchip Technology Inc. PIC16C745/765 overhead (moving the ADRES to the desired location). The appropriate analog input channel must be selected and the minimum acquisition done before the “ ...
Page 98
... PIC16C745/765 NOTES: DS41124C-page 98 Preliminary 2000 Microchip Technology Inc. ...
Page 99
... E4 - External clock with 4x PLL enabled. CLKOUT on OSC2 pin Note 1: All of the CP<1:0> pairs have to be given the same value to enable the code protection scheme listed. 2000 Microchip Technology Inc. PIC16C745/765 One is the Oscillator Start-up Timer (OST), intended to keep the chip in RESET until the crystal oscillator is sta- ble ...
Page 100
... After power-up, a PLL settling time of less than T is required. PLLRT Preliminary CERAMIC RESONATORS Freq OSC1 OSC2 CAPACITOR SELECTION FOR CRYSTAL OSCILLATOR Crystal Cap. Range Cap. Range Freq INT , using an external 6 MHz INT 2000 Microchip Technology Inc. ...
Page 101
... PD bits are set or cleared differently in different RESET situations as indicated in Table 13-4. These bits are used in software to determine the nature of the RESET. See Table 13-7 for a full description of RESET states of all registers. 2000 Microchip Technology Inc. PIC16C745/765 13.2.6 E4 MODE In E4 mode, a PLL module is switched on in-line with the clock provided to OSC1 ...
Page 102
... Reset MCLR SLEEP WDT Time-out Module Reset Power-on Reset V rise DD detect V DD Brown-out Reset OST/PWRT OST 10-bit Ripple counter OSC1 PWRT Dedicated 10-bit Ripple counter On-chip RC OSC DS41124C-page 102 Enable PWRT Enable OST Preliminary S Chip Reset Q R 2000 Microchip Technology Inc. ...
Page 103
... OSC1 input) after the PWRT delay. This ensures that the crystal oscillator or resona- tor has started and stabilized. The OST time-out is invoked only for HS mode and only on Power-on Reset or wake-up from SLEEP. 2000 Microchip Technology Inc. PIC16C745/765 13.4.4 BROWN-OUT RESET (BOR ...
Page 104
... SLEEP PWRTE = 1 1024 T 1024 T OSC OSC PLLRT PLLRT 1024 T 1024 T OSC OSC PLLRT PLLRT PCON Register ---- --0x ---- --uu ---- --uu ---- --uu ---- --uu ---- --u0 ---- --uu Value on: Value on all Bit 0 POR, BOR other Resets C 0001 1xxx 000q quuu BOR ---- --qq ---- --uu 2000 Microchip Technology Inc. ...
Page 105
... Note 1: One or more bits in INTCON, PIR1 and/or PIR2 will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h). 3: See Table 13-5 for RESET value for specific condition. 4: PIC16C765 only. 2000 Microchip Technology Inc. PIC16C745/765 MCLR Resets ...
Page 106
... Note 1: One or more bits in INTCON, PIR1 and/or PIR2 will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h). 3: See Table 13-5 for RESET value for specific condition. 4: PIC16C765 only. DS41124C-page 106 MCLR Resets WDT Reset ...
Page 107
... The latency is the same for one or two cycle instructions. Individual interrupt flag bits are set, regardless of the status of their corresponding mask bit or the GIE bit. 2000 Microchip Technology Inc. PIC16C745/765 Note interrupt occurs while the Global ...
Page 108
... The following table shows the interrupts for each device. Device T0IF INTF RBIF PSPIF PIC16C745 Yes Yes Yes PIC16C765 Yes Yes Yes Note 1: PIC16C765 only. DS41124C-page 108 (2) T OST Interrupt Latency Processor in SLEEP PC+2 PC Inst( Dummy cycle Inst( ...
Page 109
... W_TEMP,F ; SWAPF W_TEMP,W ; swapf loads W without affecting STATUS flags RETFIE 2000 Microchip Technology Inc. PIC16C745/765 13.7 Context Saving During Interrupts During an interrupt, only the PC is saved on the stack. At the very least, W and STATUS should be saved to preserve the context for the interrupted program. All registers that may be corrupted by the ISR, such as PCLATH or FSR, should be saved ...
Page 110
... CP0 PWRTE WDTE T0CS T0SE PSA PS2 Preliminary can be realized. WDT = Min., Temperature = Max., and DD PS<2:0> To TMR0 MUX (Figure 6-1) PSA Value on Value on Bit 1 Bit 0 All Other POR, BOR Resets PLL FOSC0 PS1 PS0 1111 1111 1111 1111 2000 Microchip Technology Inc. ...
Page 111
... SLEEP: 1. TMR1 interrupt. Timer1 must be operating as an asynchronous counter. 2. USB interrupt. 3. CCP capture mode interrupt. 4. Parallel slave port read or write (PIC16C765 only). 5. A/D conversion (when A/D clock source is dedi- cated internal oscillator). 6. USART (Synchronous Slave mode). 2000 Microchip Technology Inc. PIC16C745/765 Other peripherals cannot generate interrupts, since during SLEEP, no on-chip Q clocks are present ...
Page 112
... FIGURE 13-9: TYPICAL IN-CIRCUIT SERIAL External Connector Signals + CLK Data I/O Preliminary (2) 0004h 0005h Inst(0004h) Inst(0005h) Dummy cycle Inst(0004h (see programming IL IHH PROGRAMMING CONNECTION To Normal Connections PIC16CXX MCLR/V PP RB6 RB7 Normal Connections 2000 Microchip Technology Inc. ...
Page 113
... Assigned to < > Register bit field In the set of i talics User defined term (font is courier) 2000 Microchip Technology Inc. PIC16C745/765 The instruction set is highly orthogonal and is grouped into three basic categories: • Byte-oriented operations • Bit-oriented operations • Literal and control operations ...
Page 114
... Z 1,2 ffff 1,2,3 ffff Z 1,2 ffff 1,2,3 ffff Z 1,2 ffff Z 1,2 ffff ffff 0000 C 1,2 ffff C 1,2 ffff C,DC,Z 1,2 ffff 1,2 ffff Z 1,2 ffff 1,2 ffff 1,2 ffff 3 ffff 3 ffff C,DC,Z kkkk Z kkkk kkkk TO PD 0100 , kkkk Z kkkk kkkk 1001 kkkk 1000 TO PD 0011 , C,DC,Z kkkk Z kkkk Mid-Range MCU Family ™ 2000 Microchip Technology Inc. ...
Page 115
... Operation: (W) .AND. (k) (W) Status Affected: Z Description: The contents of W register are AND’ed with the eight bit literal 'k'. The result is placed in the W register. 2000 Microchip Technology Inc. PIC16C745/765 ANDWF AND W with f Syntax: [label] ANDWF Operands 127 d Operation: (W) .AND. (f) ...
Page 116
... Clear Watchdog Timer Syntax: [ label ] CLRWDT Operands: None Operation: 00h 0 WDT prescaler Status Affected: TO, PD Description: CLRWDT instruction resets the Watchdog Timer. It also resets the prescaler of the WDT. Status bits TO and PD are set. Preliminary f 127 (f) (W) WDT 2000 Microchip Technology Inc. ...
Page 117
... W register. If ’d’ the result is placed back in reg- ister ’f’. If the result is 1, the next instruc- tion is executed. If the result is 0, then a NOP is executed instead making instruction. CY 2000 Microchip Technology Inc. PIC16C745/765 GOTO Unconditional Branch Syntax: [ label ] Operands ...
Page 118
... MOVWF Move Syntax: [ label ] Operands Operation: (W) Status Affected: None Description: Move data from W register to reg- ister 'f'. NOP No Operation Syntax: [ label ] Operands: None Operation: No operation Status Affected: None Description: No operation. Preliminary MOVLW k 255 MOVWF f 127 (f) NOP 2000 Microchip Technology Inc. ...
Page 119
... TOS PC Status Affected: None Description: Return from subroutine. The stack is POPed and the top of the stack (TOS) is loaded into the program counter. This is a two cycle instruction. 2000 Microchip Technology Inc. PIC16C745/765 RLF Rotate Left f through Carry Syntax: [ label ] Operands ...
Page 120
... Exclusive OR W with f Syntax: [label] Operands 127 d [0,1] Operation: (W) .XOR. (f) Status Affected: Z Description: Exclusive OR the contents of the W register with register 'f the result is stored in the W register the result is stored back in register 'f'. Preliminary XORLW k 255 W) XORWF f,d destination) 2000 Microchip Technology Inc. ...
Page 121
... A full featured editor • A project manager • Customizable tool bar and key mapping • A status bar • On-line help 2000 Microchip Technology Inc. PIC16C745/765 MPLAB allows you to: • Edit your source files (either assembly or ‘C’) • One touch assemble (or compile) and download ...
Page 122
... Running at full speed enables testing hardware in real-time. The MPLAB-ICD is also a programmer for the flash PIC16F87X family. Preliminary ® in two versions; PIC16C5X, PIC16C6X, built into the 2000 Microchip Technology Inc. ...
Page 123
... Some of the features include an RS-232 interface, a potentiometer for simulated analog input, push-button switches and eight LEDs connected to PORTB. 2000 Microchip Technology Inc. PIC16C745/765 15.12 PICDEM-2 Low-Cost PIC16CXX Demonstration Board The PICDEM simple demonstration board that supports the PIC16C62, PIC16C64, PIC16C65, PIC16C73 and PIC16C74 microcontrollers ...
Page 124
... K L evaluation and programming tools support EE OQ Microchips HCS Secure Data Products. The HCS eval- uation kit includes an LCD display to show changing codes, a decoder to decode transmissions, and a pro- gramming interface to program test transmitters. DS41124C-page 124 PIC17C756, Preliminary 2000 Microchip Technology Inc. ...
Page 125
... PIC16C6X á á á á PIC16C5X á á á PIC14000 á á á á PIC12CXXX Tools Software Emulators 2000 Microchip Technology Inc. PIC16C745/765 á á á á á á á á á á á á á á á á á ...
Page 126
... PIC16C745/765 NOTES: DS41124C-page 126 Preliminary 2000 Microchip Technology Inc. ...
Page 127
... Exposure to maximum rating conditions for extended periods may affect device reliability. 2000 Microchip Technology Inc. (except V , MCLR and RA4) .......................................... -0. ...
Page 128
... PIC16C745/765 FIGURE 16-1: VALID OPERATING REGIONS, FREQUENCY ON F -40°C TA +85°C 5.5 V 5.25 V 4.35 V 4.0 V DS41124C-page 128 , INT 24 MHz Frequency Preliminary 2000 Microchip Technology Inc. ...
Page 129
... This current should be added to the base measurement Module differential currents measured at F 2000 Microchip Technology Inc. PIC16C745/765 Standard Operating Conditions (unless otherwise stated) Operating temperature -40° Min Typ† ...
Page 130
... USB suspended 8.5 mA 4.35V - + 1.6 mA 4.35V - + -3.0 mA 4.35V - + -1.3 mA 4.35V - +85 C RA4 pin In HS mode when external clock is used to drive OSC1. + 20% (See Section 10.7.1) 2000 Microchip Technology Inc. ...
Page 131
... CCP1 ck CLKOUT SDI do SDO dt Data in io I/O port mc MCLR Uppercase letters and their meanings Fall H High I Invalid (Hi-impedance) L Low 2000 Microchip Technology Inc. PIC16C745/765 T Time osc OSC1 SCK T0CKI t1 T1CKI Period R Rise V Valid Z Hi-impedance ...
Page 132
... TEMPERATURE AND VOLTAGE SPECIFICATIONS - AC Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C AC CHARACTERISTICS Operating voltage V Section 16.2. FIGURE 16-2: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS Load condition 1 V Pin Note 1: PIC16C765 only. DS41124C-page 132 T +85°C A range as described in DC spec Section 16.1 and DD Load condition ...
Page 133
... Note 1: F represents the internal clock signal. F INT equals CLKIN if the PLL is enabled. T OSC mode, PLL disabled OSC1 in EC mode with PLL disabled. INT 2000 Microchip Technology Inc. PIC16C745/765 equals F or CLKIN if the PLL is disabled. F ...
Page 134
... MHz H4 osc mode 41 — osc modes 167 — 167 ns E4 osc mode 41 — osc modes 167 — 167 ns H4 osc mode 167 — — — oscillator — — oscillator Preliminary = 4/F INT 2000 Microchip Technology Inc. ...
Page 135
... These parameters are for design guidance only and are not tested. ††These parameters are asynchronous events not related to any internal clock edge. Note 1: Measurements are taken in EC Mode where CLKOUT output OSC1 when PLL is disabled. INT 2000 Microchip Technology Inc. PIC16C745/765 ...
Page 136
... OSC 28 72 132 ms — — 2.1 s 100 — — s — 1.4 — ms Preliminary 34 Conditions V = 5V, -40°C to +85° 5V, -40°C to +85° OSC1 period OSC V = 5V, -40°C to +85° (D005) DD VDD T = OSC1 period OSC 2000 Microchip Technology Inc. ...
Page 137
... Delay from external clock edge to timer increment TMR * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. 2000 Microchip Technology Inc. PIC16C745/765 41 40 ...
Page 138
... Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. DS41124C-page 138 Min Typ† 0 — — 0 — — — — 10 — 10 Preliminary Max Units Conditions — ns — ns — ns — ns — prescale value (1, 2000 Microchip Technology Inc. ...
Page 139
... FIGURE 16-10: PARALLEL SLAVE PORT TIMING (PIC16C765) RE2/CS RE0/RD RE1/WR RD<7:0> 64 Note: Refer to Figure 16-2 for load conditions. TABLE 16-7: PARALLEL SLAVE PORT REQUIREMENTS Param No. Sym 62 Data in valid before (setup time 63 data–in invalid (hold time ...
Page 140
... DS41124C-page 140 121 122 Characteristic Min — — — 125 126 Min Typ† 15 — (DT setup time) (DT hold time) 15 — Preliminary Typ† Max Units Conditions — — — Max Units Conditions — ns — ns 2000 Microchip Technology Inc. ...
Page 141
... When A/D is off, it will not consume any current other than minor leakage current. The power-down current spec includes any such leakage from the A/D module current is from the RA3 pin or the V REF 3: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes. 2000 Microchip Technology Inc. PIC16C745/765 Min Typ† Max — — 8 bits — ...
Page 142
... LSb (i.e., 20 5.12V) from the last sampled voltage (as stated HOLD — If the A/D clock source is selected as RC, a time added before the A/D clock starts. This allows the SLEEP instruction to be executed 2000 Microchip Technology Inc. ...
Page 143
... Voltage Output Low OL V Voltage Output High OH V USB Voltage Output USB Note 1: Parameters are per USB Specification 1.1. No Microchip specific parameter numbers exist (per the PICmicro™ Mid-Range Reference Manual, DS33023. 2000 Microchip Technology Inc. PIC16C745/765 66.7ns 6MHz 60ns min 4.6V -1.0V 4ns min 20ns max , GND, cable shield or any other signal ...
Page 144
... PIC16C745/765 NOTES: DS41124C-page 144 Preliminary 2000 Microchip Technology Inc. ...
Page 145
... The data presented in this section is a statistical summary of data collected on units from different lots over a period of time. “Typical” represents the mean of the distribution. FIGURE 17-1: TYPICAL I vs 25.00 20.00 15.00 10.00 5.00 4.35 FIGURE 17-2: TYPICAL I vs 160.00 140.00 120.00 100.00 80.00 4.35 2000 Microchip Technology Inc 24MHz) DD INT 5.00 5.25 V (V) DD (USB SUSPENDED, WDT DISABLED) DD 5.00 5.25 V (V) DD Preliminary PIC16C745/765 DS41124C-page 145 ...
Page 146
... PIC16C745/765 FIGURE 17-3: DC LOAD LINES FOR USB REGULATOR OUTPUT ( Load Current (mA) DS41124C-page 146 USB Preliminary ) 2000 Microchip Technology Inc. ...
Page 147
... Standard OTP marking consists of Microchip part number, year code, week code and traceability code. For OTP marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price. 2000 Microchip Technology Inc. PIC16C745/765 Example ...
Page 148
... XXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXX YYWWNNN 44-Lead TQFP XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN 44-Lead PLCC XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN 40-Lead CERDIP Windowed XXXXXXXXXXX XXXXXXXXXXX XXXXXXXXXXX YYWWNNN DS41124C-page 148 Example PIC16C765-I/P 9917017 Example PIC16C765-I/PT 9917017 Example PIC16C765-I/L 9917017 Example Preliminary PIC16C745-I/JW 9905017 2000 Microchip Technology Inc. ...
Page 149
... Mold Draft Angle Bottom * Controlling Parameter § Significant Characteristic Notes: Dimension D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MO-095 Drawing No. C04-070 2000 Microchip Technology Inc Units INCHES* MIN NOM ...
Page 150
... E .394 .407 .420 E1 .288 .295 .299 D .695 .704 .712 h .010 .020 .029 L .016 .033 .050 .009 .011 .013 B .014 .017 .020 Preliminary A2 MILLIMETERS MIN NOM MAX 28 1.27 2.36 2.50 2.64 2.24 2.31 2.39 0.10 0.20 0.30 10.01 10.34 10.67 7.32 7.49 7.59 17.65 17.87 18.08 0.25 0.50 0.74 0.41 0.84 1. 0.23 0.28 0.33 0.36 0.42 0. 2000 Microchip Technology Inc. ...
Page 151
... Tip to Seating Plane Lead Thickness Upper Lead Width Lower Lead Width Overall Row Spacing § Window Diameter Lid Length Lid Width * Controlling Parameter § Significant Characteristic JEDEC Equivalent: MS-015 Drawing No. C04-084 2000 Microchip Technology Inc Units INCHES* MIN NOM MAX ...
Page 152
... E1 D 2.045 2.058 2.065 L .120 .130 .135 c .008 .012 .015 B1 .030 .050 .070 B .014 .018 .022 eB .620 .650 .680 Preliminary MILLIMETERS MIN NOM MAX 40 2.54 4.06 4.45 4.83 3.56 3.81 4.06 0.38 15.11 15.24 15.88 13.46 13.84 14.22 51.94 52.26 52.45 3.05 3.30 3.43 0.20 0.29 0.38 0.76 1.27 1.78 0.36 0.46 0.56 15.75 16.51 17. 2000 Microchip Technology Inc. ...
Page 153
... Overall Length Tip to Seating Plane Lead Thickness Upper Lead Width Lower Lead Width Overall Row Spacing § Window Diameter * Controlling Parameter § Significant Characteristic JEDEC Equivalent: MO-103 Drawing No. C04-014 2000 Microchip Technology Inc Units INCHES* MIN NOM MAX .100 A ...
Page 154
... E .463 .472 .482 D .463 .472 .482 E1 .390 .394 .398 D1 .390 .394 .398 c .004 .006 .008 B .012 .015 .017 CH .025 .035 .045 Preliminary A2 MILLIMETERS* MIN NOM MAX 44 0.80 11 1.00 1.10 1.20 0.95 1.00 1.05 0.05 0.10 0.15 0.45 0.60 0.75 1.00 0 3.5 7 11.75 12.00 12.25 11.75 12.00 12.25 9.90 10.00 10.10 9.90 10.00 10.10 0.09 0.15 0.20 0.30 0.38 0.44 0.64 0.89 1. 2000 Microchip Technology Inc. ...
Page 155
... Mold Draft Angle Bottom * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MO-047 Drawing No. C04-048 2000 Microchip Technology Inc CH1 ...
Page 156
... PIC16C745/765 NOTES: DS41124C-page 156 Preliminary 2000 Microchip Technology Inc. ...
Page 157
... RB Port Pins .............................................................. 33 Timer0/WDT Prescaler .............................................. 43 Timer2 ....................................................................... 49 USART Receive ........................................................ 83 USART Transmit ....................................................... 81 Watchdog Timer ...................................................... 110 BOR bit ............................................................................ 103 BRGH bit ........................................................................... 79 Brown-out Reset (BOR) Timing Diagram ....................................................... 136 Buffer Descriptor Table ...................................................... 68 2000 Microchip Technology Inc. PIC16C745/765 C C bit ................................................................................... 22 Capture/Compare/PWM Capture Block Diagram ................................................... 53 CCP1CON Register .......................................... 52 CCP1IF ............................................................. 53 Mode ................................................................. 53 Prescaler ........................................................... 53 CCP Timer Resources ...
Page 158
... Port RB Interrupt ............................................................. 109 PORTA ..................................................................... 20 PORTA Register ......................................................... 17 PORTB ..................................................................... 20 , 107 PORTB Register ......................................................... 17 PORTC ..................................................................... 20 PORTC Register ........................................................ 17 PORTD ..................................................................... 20 PORTD Register ........................................................ 17 PORTE ..................................................................... 20 PORTE Register ......................................................... 17 Power-down Mode (SLEEP) ........................................... 111 Preliminary , 104 , 104 , 103 , 101 , 103 , , 103 105 , 105 , 31 , 105 , 33 , 105 , 35 , 105 , 37 , 105 , 38 2000 Microchip Technology Inc. ...
Page 159
... Software Simulator (MPLAB-SIM) ................................... 122 SPBRG Register ................................................................ 18 Special Features of the CPU ............................................. 99 Special Function Registers ................................................ 17 PIC16C745/765 ......................................................... 17 SPEN bit ............................................................................ 78 SREN bit ............................................................................ 78 SSPBUF ............................................................................ 19 Stack .................................................................................. 29 Overflows .................................................................. 29 Underflow .................................................................. 29 2000 Microchip Technology Inc. PIC16C745/765 Status ................................................................................ 64 STATUS Register ..................................................... Synchronous Serial Port Module ....................................... 57 T T1CKPS0 bit ..................................................................... 45 T1CKPS1 bit ..................................................................... 45 T1CON .............................................................................. 20 T1CON Register ...
Page 160
... Wake-up from SLEEP ..................................................... 111 Watchdog Timer (WDT) ......................... 99 Timing Diagram ....................................................... 136 WDT ................................................................................ 104 Block Diagram ......................................................... 110 Period ...................................................................... 110 Programming Considerations .................................. 110 Timeout ................................................................... 105 WR pin .............................................................................. 40 WWW, On-Line Support ...................................................... bit ................................................................................... Preliminary , , , 101 104 110 2000 Microchip Technology Inc. ...
Page 161
... Microchip Products • Conferences for products, Development Systems, technical information and more • Listing of seminars and events 2000 Microchip Technology Inc. PIC16C745/765 Systems Information and Upgrade Hot Line The Systems Information and Upgrade Line provides system users a listing of the latest versions of all of Microchip's development systems software products ...
Page 162
... Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? 8. How would you improve our software, systems, and silicon products? DS41124C-page 162 Total Pages Sent FAX: (______) _________ - _________ N Literature Number: DS41124C Preliminary 2000 Microchip Technology Inc. ...
Page 163
... PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X /XX Device Temperature Package Range (1) Device PIC16C745 , PIC16C745T (1) PIC16C765 , PIC16C765T Temperature Range +85 C Package JW = Windowed CERDIP - 600 mil PT = TQFP (Thin Quad Flatpack SOIC ...
Page 164
... Use of Microchip’s products as critical com- ponents in life support systems is not authorized except with express written approval by Microchip. No licenses are con- veyed, implicitly or otherwise, under any intellectual property rights. 2002 Microchip Technology Inc. ® MCUs. Trademarks The Microchip name and logo, the Microchip logo, FilterLab, ...
Page 165
... Palazzo Taurus Colleoni 1 20041 Agrate Brianza Milan, Italy Tel: 39-039-65791-1 Fax: 39-039-6899883 United Kingdom Arizona Microchip Technology Ltd. 505 Eskdale Road Winnersh Triangle Wokingham Berkshire, England RG41 5TU Tel: 44 118 921 5869 Fax: 44-118 921-5820 03/01/02 2002 Microchip Technology Inc. ...