LMX2335L National Semiconductor Corporation, LMX2335L Datasheet - Page 12

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LMX2335L

Manufacturer Part Number
LMX2335L
Description
Pllatinum? Low Power Dual Frequency Synthesizer For Rf Personal Communications
Manufacturer
National Semiconductor Corporation
Datasheet

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Functional Description
The simplified block diagram below shows the 22-bit data register, two 15-bit R Counters and two 18-bit N Counters (intermediate
latches are not shown). The data stream is clocked (on the rising edge of Clock) into the DATA register, MSB first. The data stored
in the shift register is loaded into one of the 4 appropriate latches on the rising edge of LE. The last two bits are the Control Bits.
The DATA is transferred into the counters as follows:
PROGRAMMABLE REFERENCE DIVIDERS (RF1 AND RF2 R COUNTERS)
If the Control Bits are 00 or 01 (00 for RF2 and 01 for RF1) data is transferred from the 22-bit shift register into a latch which sets
the 15-bit R Counter. Serial data format is shown below.
15-BIT PROGRAMMABLE REFERENCE DIVIDER RATIO (R COUNTER)
Notes:
Divide R
32767
Ratio 15 14 13 12 11 10 9
Divide ratios less than 3 are prohibited.
Divide ratio: 3 to 32767
R1 to R15: These bits select the divide ratio of the programmable reference divider.
Data is shifted in MSB first.
3
4
0
0
1
R
0
0
1
R
0
0
1
Control Bits
C1
0
0
1
1
R
0
0
1
R
0
0
1
C2
0
1
0
1
R
0
0
1
12
R
0
0
1
RF2 R Counter
RF1 R Counter
RF2 N Counter
RF1 N Counter
DATA Location
R
8
0
0
1
R
7
0
0
1
R
6
0
0
1
R
5
0
0
1
R
4
0
0
1
R
3
0
1
1
R
2
1
0
1
R
01280706
1
1
0
1
01280705

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