CY2077 Cypress Semiconductor Corporation., CY2077 Datasheet - Page 2

• Manufacturer Part Number: CY2077
• Description: High-accuracy Eprom Programmable Single-pll Clock Generator
• Manufacturer: Cypress Semiconductor Corporation.

Pin Configuration
Table 1. Pin Definition - 8 Pin
Functional Description
CY2077
general-purpose, PLL-based design for use in applications such
as modems, disk drives, CD-ROM drives, video CD players,
DVD players, games, set-top boxes, and data/telecommunica-
tions.
CY2077 can generate a clock output up to 133 MHz at 5V or 100
MHz at 3.3V. It has been designed to give the customer a very
accurate and stable clock frequency with little to zero PPM error.
CY2077 contains a 12-bit feedback counter divider and 10-bit
reference counter divider to obtain a very high resolution to meet
the needs of stringent design specifications. Furthermore, there
are eight output divide options of /1, /2, /4, /8, /16, /32, /64, and
/128. The output divider can select between the PLL and crystal
oscillator output/external clock, providing a total of 16 different
options to add more flexibility in designs. TTL or CMOS duty
cycles can be selected.
Power management with the CY2077 is also very flexible. The
user can choose either a PWR_DWN, or an OE feature with
which both have integrated pull up resistors. PWR_DWN and OE
signals can be programmed to have asynchronous and
synchronous timing with respect to the output signal. There is a
weak pull down on the output that pulls CLKOUT LOW when
either the PWR_DWN or OE signal is active. This weak pull down
can easily be overridden by another clock signal in designs
where multiple clock signals share a signal path.
Multiple options for output selection, better power distribution
layout, and controlled rise and fall times enable the CY2077 to
be used in applications that require low jitter and accurate
reference frequencies.
Document Number: 38-07210 Rev. *C
Note
V
V
X
X
PWR_DWN / OE
CLKOUT
2. When using CyClocks, note that the PLL frequency range is from 50 MHz to 250 MHz for 5V V
DD
SS
D
G
frequency is determined by the selected output divider.
Pin Name
is
an
1
5,6,7
2
3
4
8
EPROM-programmable,
Pin #
Voltage supply
Ground (all the pins must be grounded)
Crystal output (leave this pin floating when external reference is used)
Crystal input or external input reference
EPROM programmable power down or output enable pin. Weak pull up
Clock output. Weak pull down
XTALOUT
Figure 1. Pin Diagram - 8 Pin Top View
XTALIN
PD/OE
high-accuracy,
V
DD
1
2
3
4
EPROM Configuration Block
Table 2. EPROM Adjustable Features
PLL Output Frequency
CY2077 contains a high-resolution PLL with 12-bit multiplier and
10-bit divider.
by the following formula:
where P is the feedback counter value and Q is the reference
counter value. P and Q are EPROM programmable values.
The calculation of P and Q values for a given PLL output
frequency is handled by the CyberClocks™ software. Refer to
““Programming Procedures”
8
7
6
5
Power management timing (synchronous or asynchronous)
Adjust
Freq.
Pin Description
Power management mode (OE or PWR_DWN)
DD
CLKOUT
V
V
V
SS
SS
SS
supply, and 50 MHz to 180 MHz for 3V V
[2]
Duty cycle levels (TTL or CMOS)
F
The output frequency of the PLL is determined
EPROM Adjustable Features
PLL
=
Reference counter value (Q)
Feedback counter value (P)
2
--------------------------- F
(
Output divider selection
•
Q
(
P
on page 12” for details.
+
+
2
)
5
)
•
REF
DD
supply. The output
CY2077
Page 2 of 14
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