STSMIA832 STMicroelectronics, STSMIA832 Datasheet - Page 8

• Manufacturer Part Number: STSMIA832
• Description: 1.8v/2.8v High Speed Dual Differential Line Receivers, Standard Mobile Imaging Architecture Smia Decoder Deserializer
• Manufacturer: STMicroelectronics

Pin configuration
Figure 7.
Table 2.
8/23
Logical Channels
Name
SOF
EOF
SOL
EOL
Frame synchronization
Each image frame begins with frame start synchronization code (SOF) and ends with frame
end synchronization code (EOF). Each line inside the frame begins with line start
synchronization code (SOL) and ends with line end synchronization code (EOL). The period
between EOL code and new SOL code is called line blanking period. Similarly, the time
between EOF code and new SOF code is called frame blanking period. The total size of one
image frame shall be a multiple of 128 bits.
In the beginning of frame and in the end of frame, line synchronization codes are replaced
by the frame synchronization codes. Synchronization signal usage is shown in Figure 4
below. Bit order of the synchronization codes is the same as for data, byte-wise LSB first.
CCP2 Synchronization codes
The purpose of logical channels is to separate different data flows, which are interleaved in
the data stream.
The DMA channel identifier number is directly encoded in the 4-byte CCP embedded sync
codes. The CCP receiver will monitor the DMA channel identifier and de-multiplex the
interleaved video streams to their appropriate DMA channel. A maximum of 8 data streams
is supported. Valid channel identifiers are 0 to 7.
X = channel number 0 to 7.
Synchronization codes as per SMIA specifications
FFH 00H 00H 0XH (to) FFH 00H 00H 7XH
Synchronization Codes
FFH 00H 00H X0H
FFH 00H 00H X1H
FFH 00H 00H X2H
FFH 00H 00H X3H
Line Start Code
Line End Code
Frame Start Code
Frame End Code
DMA Channel Identifier from Channel 0 to 7
Notes
STSMIA832