ST95P04 STMicroelectronics, ST95P04 Datasheet - Page 12

• Manufacturer Part Number: ST95P04
• Description: Serial Access Spi Bus 4k 512 X 8 Eeprom
• Manufacturer: STMicroelectronics

ST95P04
Figure 13. WRSR: Write Status Register Sequence
POWER ON STATE
After a Power up the ST95P04 is in the following
state:
– The device is in the low power standby state.
– The chip is deselected.
– The chip is not in hold condition.
– The write enable latch is reset.
– BP1 and BP0 are unchanged (non-volatile
DATA PROTECTION AND PROTOCOL SAFETY
– All inputs are protected against noise, see Ta-
– Non valid S and HOLD transitions are not
– S must come high at the proper clock count in
12/16
bits).
ble 3.
taken into account.
order to start a non-volatile write cycle (in the
memory array or in the cycle status register).
S
C
D
Q
0
1
HIGH IMPEDANCE
INSTRUCTION
2
3
4
5
6
7
8
– Access to the memory array during non-vola-
– After either of the following operations
– The write enable latch is reset upon power-up.
– The write enable latch is reset when W is
INITIAL DELIVERY STATE
The device is delivered with the memory array in a
fully erased state (all data set at all "1’s" or FFh).
The block protect bits are initialized to 00.
9 10 11 12 13 14 15
STATUS REG.
The Chip Select S must rise during the clock
pulse following the introduction of a multiple of
8 bits.
tile programming cycle is cancelled and the
chip is automatically deselected; however, the
programming cycle continues.
(WREN, WRDI, RDSR) is completed, the chip
enters a wait state and waits for a deselect.
brought low.
AI01434