BU9832GUL-W ROHM Co. Ltd., BU9832GUL-W Datasheet
BU9832GUL-W
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BU9832GUL-W Summary of contents
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Silicon Monolithic Integrated Circuit ◇PRODUCT 1,024×8 bit Electrically Erasable PROM ◇PART NUMBER BＵ9832ＧＵＬ－Ｗ ◇PHYSICAL DIMENSION Fig.1 (Plastic Mold) ◇BLOCK DIAGRAM Fig.2 ◇USE General purpose ◇FEATURES ・ 1,024 words × 8 bits architecture serial EEPROM ・Wide operating voltage range (1.8V～5.5V) ...
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OPERATING CONDITION Parameter Symbol Rating Supply Voltage V 1.8～5.5 cc Input Voltage V 0～V IN ◇DC OPERATING CHARACTERISTICS (Unless otherwise specified Ta=-40～85℃､V Parameter Symbol “H” Input Voltage1 V IH1 “L” Input Voltage1 V IL1 “L” Output Voltage1 V OL1 ...
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LOT NO. Fig.1 PHYSICAL DIMENSION REV. B 3/13 ...
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... CONFIGURATION INSTRUCTION DECODE CS CONTROL CLOCK SCK GENERATION INSTRUCTION SI REGISTER HOLD WP SO ◇PIN CONFIGURATION Ｆｉｇ-3 BU9832GUL-W （bottom view） ◇PIN NAME Land No. PIN NAME GND SCK Vcc HOLD C3 VOLTAGE DETECTION WRITE INHIBITION ADDRESS ADDRESS ...
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SYNCHRONOUS DATA TIMING tCS CSB tSCKS SCK data is latched into the chip at the rising edge of SCK clock. Address and data must be transferred from MSB. CSB SCK data toggles at ...
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OPERATING CHARACTERISTICS （Ｔａ＝-40～85℃） Parameter Symbol SCK clock Frequency fSCK SCK High Time tSCKWH SCK Low Time tSCKWL CS High Time tCS CS Setup Time tCSS CS Hold Time tCSH SCK Setup Time tSCKS SCK Hold Time tSCKH SI Setup ...
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Description ○Status Register The device has status register. Status register consists of 8bits and is shown following parameters. 3bits(WPEN, BP0 and BP1) are set by “Write Status Register” commands, which are non-volatile. Specification of endurance and data retention are ...
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CODE Instruction WREN Write enable WRDI Write disable READ Read data from memory array WRITE Write data to memory array RDSR Read status register WRSR Write status register Operation Op.Code 0000 0110 0000 0100 0000 0011 0000 0010 0000 ...
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CHART 1.WREN （WRITE ENABLE） CSB SCK Hi-Z SO Fig.7 WRITE ENABLE CYCLE TIMING CSB SCK Hi-Z SO Fig.8 WRITE DISABLE CYCLE TIMING 2.WRDI (WRITE DISABLE) The device has both ...
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CSB SCK Hi-Z SO The data stored in the memory are clocked out after “Read” instruction is received. After CS goes low, the address need to ...
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CSB SCK Hi-Z SO This “Write” command writes 8bits of data into the specified address. After CS goes low,the address need to be sent following ...
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RDSR (READ STATUS REGISTER) CSB SCK Hi-Z Fig.11 READ STATUS REGISTER CYCLE TIMING The data stored in the status register is clocked out after “Read Status Register” instruction is ...
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STATUS RESISTER) CSB SCK Hi-Z SO Fig.12 WRITE STATUS REGISTER WRITE CYCLE TIMING This “Write Status Register” command writes the data, two (BP1, BP0) of the eight bits, into ...
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