BU9833GUL-W ROHM Co. Ltd., BU9833GUL-W Datasheet
BU9833GUL-W
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BU9833GUL-W Summary of contents
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... Silicon Monolithic Integrated Circuit ◇PRODUCT 256×8 bit Electrically Erasable PROM ◇PART NUMBER BU9833GUL-W ◇PHYSICAL DIMENSION Fig.-1 ◇BLOCK DIAGRAM Fig.-2 ◇USE General purpose ◇FEATURES ・ 256 registers × 8 bits serial architecture ・Single power supply (1.7V～5.5V) ・Two wire serial interface ・Self-timed write cycle with automatic erase ・ ...
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OPERATING CONDITION Parameter Symbol Supply Voltage V CC Input Voltage V IN ◇DC OPERATING CHARACTERISTICS (Unless otherwise specified Ta=-40～85℃､V Parameter Symbol “H” Input Voltage1 V IH1 “L” Input Voltage1 V IL1 “H” Input Voltage2 V IH2 “L” Input Voltage2 ...
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... Fig.-1 PHYSICAL DIMENSION （VCSP50L1） （Unit : mm） ◇BLOCK DIAGRAM Product Name：BU9833GUL-W 9833 LOT NO. REV. A 3/12 ...
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... VCC GND 8bit ADDRESS DECODER A2 CONTOROL LOGIC HIGH VOLTAGE GEN. ◇PIN CONFIGURATION Fig.-3 BU9833GUL－Ｗ（bottom view） ◇PIN NAME Land No. PIN NAME C2 V ＣＣ GND A2 SCL A1 SDA IN/OUT *1 An open drain output requires a pull-up resister. ◇AC OPERATING CHARACTERISTICS (Unless otherwise specified Ta=-40～85℃､V 2 Kbit EEPROM ARRAY SLAVE・ ...
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Parameter Clock Frequency Data Clock High Period Data Clock Low Period SDA and SCL Rise Time ※1 SDA and SCL Fall Time ※1 Start Condition Hold Time Start Condition Setup Time Input Data Hold Time Input Data Setup Time Output ...
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DATA TIMING SCL t :STA HD SDA (IN) t BUF SDA (OUT) SCL t :STA SU SDA Fig.-4 SYNCHRONOUS DATA TIMING ○ SDA data is latched into the chip at the rising edge of SCL clock. ○ Output date ...
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TIMING SCL DATA( SDA ACK WP t ：WP SU Fig-6(a) WP TIMING OF THE WRITE OPERATION SCL DATA( SDA ACK WP Fig-6(b) WP TIMING OF THE WRITE CANCEL OPERATION ○For the WRITE operation, WP must ...
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CONDITION (RECOGNITION OF START BIT) ・All commands are proceeded by the start condition, which is a HIGH to LOW transition of SDA when SCL is HIGH. ・The device continuously monitors the SDA and SCL lines for the start condition ...
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The transmitter device will release the bus after transmitting eight bits. (When inputting the slave address in the write or read operation, transmitter is μ-COM. When outputting the data ...
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SLAVE R ADDRESS T SDA LINE Fig.-8 BYTE WRITE CYCLE TIMING ○By using this command, the data is programed into the indicated word address. ○When the ...
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READ SLAVE R ADRESS T SDA LINE Fig.-10 CURRENT READ CYCLE TIMING ○ In case that the previous operation is Random or Current Read (which includes Sequential Read respectively), the internal address ...
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SLAVE A R ADDRESS D T SDA LINE Fig.-12 SEQUENTIAL READ CYCLE TIMING ○If an Acknowledge is detected, and no STOP ...
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No copying or reproduction of this document, in part or in whole, is permitted without the consent of ROHM Co.,Ltd. The content specified herein is subject to change for improvement without notice. The content specified herein is for the purpose ...