LTC2704-14 Linear Technology Corporation, LTC2704-14 Datasheet - Page 8

• Manufacturer Part Number: LTC2704-14
• Description: Ltc2704-14 - Quad 14-bit Voltage Output Softspan Dac With Readback
• Manufacturer: Linear Technology Corporation

PI FU CTIO S
LTC2704
LTC2704-16/LTC2704-14/LTC2704-12
V
Typically –15V. –4.5V to –16.5V Range.
REFG1 (Pin 2): Reference 1 Ground. High impedance
input, does not carry supply currents. Tie to clean analog
ground.
AGNDA (Pin 3): DAC A Signal Ground. High impedance
input, does not carry supply currents. Tie to clean analog
ground.
VOSA (Pin 4): Offset Adjust for DAC A. Nominal input
range is ±5V. V
±2.5V modes]. See Operation section.
C1A (Pin 5): Feedback Capacitor Connection for DAC A
Output. This pin provides direct access to the negative
input of the channel A output amplifier.
OUTA (Pin 6): DAC A Voltage Output Pin. For best load
regulation, this open-loop amplifier output is connected to
RFBA as close to the load as possible.
RFBA (Pin 7): DAC A Output Feedback Resistor Pin.
TYPICAL PERFOR A CE CHARACTERISTICS
8
–
U
(Pins 1, 8, 15, 22, 31, 36): Analog Negative Supply,
U
1µV/DIV
OS
(DAC A) = –0.01• V(VOSA) [0V to 5V,
V + /V
V
0V TO 5V RANGE
CODE = 0
0.1Hz to 10Hz Noise
REF
U
–
= 5V
= ±15V
W
1s/DIV
U
2704 G16
LDAC (Pin 9): Asynchronous DAC Load Input. When
LDAC is a logic low, all DACs are updated.
CS/LD (Pin 10): Synchronous Chip Select and Load Pin.
SDI (Pin 11): Serial Data Input. Data is clocked in on the
rising edge of the serial clock when CS/LD is low.
SRO (Pin 12): Serial Readback Data Output. Data is clocked
out on the falling edge of SCK. Readback data begins clock-
ing out after the last address bit A0 is clocked in.
SCK (Pin 13): Serial Clock.
CLR (Pin 14): Asynchronous Clear Pin. When this pin is
low, all code and span B2 registers are cleared to zero. All
DAC outputs are cleared to zero volts.
RFBD (Pin 16): DAC D Voltage Output Feedback Resistor
Pin.
OUTD (Pin 17): DAC D Voltage Output Pin. For best load
regulation, this open-loop amplifier output is connected to
RFBD as close to the load as possible.
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
0
V
vs Logic Voltage
CC
0.5
Supply Current
1.0 1.5
LOGIC VOLTAGE (V)
2.0
2.5
V
SCK, SDI, CS/LD, LDAC
CLR TIED TOGETHER
DD
3.0
= 5V
3.5
4.0
4.5 5.0
2704 G17
2704f