S3092 AMCC (Applied Micro Circuits Corp), S3092 Datasheet
S3092
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S3092 Summary of contents
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... HUDSON S3092 (19203) GENERAL DESCRIPTION The S3092 SONET/SDH receiver chip is a fully inte- grated deserializer/CDR with SONET OC-192 with FEC and Digital Wrapper (9.953 Gbps to 10.709 Gbps) rate capability. The S3092 receives an OC-192 scrambled NRZ signal and recovers the clock from the data. The ...
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... S3092 – SONET/SDH/ATM OC-192 1:16 Receiver with CDR and Postamp FEATURES .............................................................................................................................................................. 1 APPLICATIONS ...................................................................................................................................................... 1 GENERAL DESCRIPTION ...................................................................................................................................... 1 CONTENTS ............................................................................................................................................................. 2 LIST OF FIGURES .................................................................................................................................................. 3 LIST OF TABLES .................................................................................................................................................... 3 SONET OVERVIEW ................................................................................................................................................ 4 Data Rates and Signal Hierarchy ...................................................................................................................... 4 Frame and Byte Boundary Detection ................................................................................................................ 4 S3092 OVERVIEW .................................................................................................................................................. 6 S3092 ARCHITECTURE/FUNCTIONAL DESIGN .................................................................................................. 7 Receiver Description ......................................................................................................................................... 7 Postamp ............................................................................................................................................................ 7 Clock Recovery ................................................................................................................................................. 7 Lock Detect ........................................................................................................................................................ 7 Serial-to-Parallel Converter ...
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... Figure 7. Parallel Data Output Delay from POCLK ................................................................................................ 17 Figure 8. Data Invalid Window ............................................................................................................................... 18 Figure 9. S3092 LVDS Driver to LVDS Input, Reference Only .............................................................................. 18 Figure 10. -5.2 V ECL Post Amp to S3092 Input DC Coupled Termination, Reference Only ................................ 19 Figure 11. -5.2 V ECL Post Amp to S3092 Input AC Coupled Termination, Reference Only ................................ 19 Figure 12. External Loop Filter ............................................................................................................................... 19 Figure 13 ...
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... SPE bytes is repeated nine times in each frame. Frame and byte boundaries are detected using the A1 and A2 bytes found in the transport overhead. (See Figure 3.) The S3092 does not provide A1/A2 detection or alignment to. For more details on SONET operations, refer to the Bellcore SONET standard document. ...
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... S3092 – SONET/SDH/ATM OC-192 1:16 Receiver with CDR and Postamp Figure 3. STS-192 Frame Format 192 A1 Bytes Transport Overhead 576 Columns 576 5,184 bytes A2 A2 192 A2 Bytes Synchronous Payload Envelope 16,704 Columns 16,704 150,336 bytes 125 µsec Revision A – February 22, 2002 ...
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... SONET equipment, which consists primarily of the serial transmit interface and the serial receive inter- face. The chip includes clock and data recovery, serial-to-parallel conversion and system timing. The sequence of operations of the S3092 is as follows: Receiver operations: 1. Serial input to limiting postamp 2. Clock and data recovery 3 ...
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... On the falling edge of the POCLK, the data in the holding register is transferred to an output holding register which drives POUTP/N[15:0]. Power Sequencing In order to avoid latch up required that the -5.2 V power be applied to the S3092 for a minimum before the application of 3.3 V power. 7 ...
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... S3092 – SONET/SDH/ATM OC-192 1:16 Receiver with CDR and Postamp Table 2. Input Pin Description and Assignment Pin Name Level I/O Pin # SERDATIP Diff.CML I G1 SERDATIN J1 REFCLKP Diff.ECL I B1 REFCLKN C1 CAP1 Analog I B4 CAP2 C4 LCKREFN LVTTL I C14 SDN ECL I A9 RSTB LVTTL I A7 TESTB ...
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... S3092 – SONET/SDH/ATM OC-192 1:16 Receiver with CDR and Postamp Table 3. Output Pin Description and Assignment Pin Name Level I/O POCLKP LVDS O POCLKN POUTP0 LVDS O POUTN0 POUTP1 POUTN1 POUTP2 POUTN2 POUTP3 POUTN3 POUTP4 POUTN4 POUTP5 POUTN5 POUTP6 POUTN6 POUTP7 POUTN7 POUTP8 POUTN8 POUTP9 ...
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... S3092 – SONET/SDH/ATM OC-192 1:16 Receiver with CDR and Postamp Table 4. Common Pin Description and Assignment Pin Name Level VCCDIG +3 VCCLVDS +3.3 V C9, H13, M3, M6, M13 DGND GND = 0 V A8, A10, A13, A14, B7, B14, C10, E13, L14, M4, M7, M10, N1, N10, P1, P2, P11, P12, P13, P14 VCCLVTTL +3 ...
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... S3092 – SONET/SDH/ATM OC-192 1:16 Receiver with CDR and Postamp Figure 5. S3092 Pinout AGND AGND VEE FILTER AGND B REFCLKP AGND AGND CAP1 C REFCLKN AGND AGND CAP2 VEE D AGND REFCLK E AGND AVEE F AGND AGND G SERDATIP H AGND AGND J SERDATIN K AGND AGND L AGND ...
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... S3092 – SONET/SDH/ATM OC-192 1:16 Receiver with CDR and Postamp Figure 6. S3092 Package Table 5. Thermal Management Package Max Power Device S3092 Note: See Application Note for simulation results, thermal management suggestions, and thermal profile for package attachment. 12 (70°C Ambient) 2.68 W 20.5 °C/W Revision A – February 22, 2002 DEVICE SPECIFICATION Θ ...
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... S3092 – SONET/SDH/ATM OC-192 1:16 Receiver with CDR and Postamp Table 6. Performance Specifications Parameter Nominal VCO Center Frequency Reference Clock Frequency Tolerance SERDATIP/N Input Return Loss (S 11 (when driven differentially) Capture Range Acquisition Lock Time Reference Clock Input Duty Cycle Reference Clock Rise and Fall Times ...
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... LVTTL Output Current per pin Electrostatic Discharge (ESD) Ratings The S3092 is rated to the following voltages based on the human body model: 1. All pins are rated at 100 Volts. Standards for ESD protection should be adhered to when handling the devices to ensure that they are not damaged. The standards to be used are defined in ANSI standard ANSI/ESD S20.20-1999, “ ...
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... S3092 – SONET/SDH/ATM OC-192 1:16 Receiver with CDR and Postamp Table 9. Internally Biased Differential CML Input DC Characteristics Parameters Description ∆V Differential Input Voltage Swing INDIFF ∆V Single-Ended Input Voltage Swing INSINGLE (while driven differentially) R Differential Input Resistance DIFF V Input High Voltage IH V Input Low Voltage IL Table 10 ...
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... S3092 – SONET/SDH/ATM OC-192 1:16 Receiver with CDR and Postamp Table 13. LVTTL Output DC Characteristics Parameters Description V Output High Voltage OH V Output Low Voltage OL Table 14. AC Characteristics Symbol Parameter J Jitter Tolerance TOL L Consecutive Identical Digits CID RX622MCK C POCLKP/N / RX622MCKP/N DUTY Duty Cycle T POCLKP/N Rise Time ...
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... S3092 – SONET/SDH/ATM OC-192 1:16 Receiver with CDR and Postamp Table 15. Internally Biased Differential ECL Input DC Characteristics Parameters Description ∆V Differential Input Voltage Swing INDIFF ∆V Single-ended Input Voltage Swing INSINGLE R Differential Input Resistance DIFF V Input High Voltage IH V Input Low Voltage IL Table 16 ...
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... Digital Wrapper (OTU2) Figure 9. S3092 LVDS Driver to LVDS Input, Reference Only +3 AMCC: POCLK_P OIF: RXCLK_P T ...
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... S3092 – SONET/SDH/ATM OC-192 1:16 Receiver with CDR and Postamp Figure 10. -5.2 V ECL Post Amp to S3092 Input DC Coupled Termination, Reference Only 0 V -5.2 V POST AMPLIFIER Figure 11. -5.2 V ECL Post Amp to S3092 Input AC Coupled Termination, Reference Only 0 V -5.2 V POST AMPLIFIER Figure 12. External Loop Filter Zo=50 Ω ...
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... S3092 – SONET/SDH/ATM OC-192 1:16 Receiver with CDR and Postamp Figure 13. Differential Voltage Measurement V(+) WRT GND V(-) WRT GND 0 V V(+) WRT V(-) 0 V Note: WRT = with respect to Figure 14. Jitter Tolerance UIpp 20 Revision A – February 22, 2002 DEVICE SPECIFICATION V ISINGLE V IDIFF = ISINGLE GR-1377 Limit S3092 Capability ...
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... S3092 – SONET/SDH/ATM OC-192 1:16 Receiver with CDR and Postamp Prefix S - Integrated Circuit Phone: (858) 450-9333 — (800) 755-2622 — Fax: (858) 450-9885 Phone: (858) 450-9333 — (800) 755-2622 — Fax: (858) 450-9885 AMCC reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied on is current ...