ACS573MS Intersil Corporation, ACS573MS Datasheet
ACS573MS
Manufacturer Part Number
ACS573MS
Description
Radiation Hardened Octal Three-state Transparent Latch
Manufacturer
Intersil Corporation
Datasheet
1.ACS573MS.pdf
(4 pages)
January 1996
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
Features
• Devices QML Qualified in Accordance with MIL-PRF-38535
• Detailed Electrical and Screening Requirements are Contained in
• 1.25 Micron Radiation Hardened SOS CMOS
• Total Dose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >300K RAD (Si)
• Single Event Upset (SEU) Immunity: <1 x 10
• SEU LET Threshold . . . . . . . . . . . . . . . . . . . . . . . >100 MEV-cm
• Dose Rate Upset . . . . . . . . . . . . . . . . >10
• Dose Rate Survivability . . . . . . . . . . . >10
• Latch-Up Free Under Any Conditions
• Military Temperature Range . . . . . . . . . . . . . . . . . . -55
• Significant Power Reduction Compared to ALSTTL Logic
• DC Operating Voltage Range . . . . . . . . . . . . . . . . . . . . 4.5V to 5.5V
• Input Logic Levels
• Input Current
• Fast Propagation Delay . . . . . . . . . . . . . . . . 17ns (Max), 12ns (Typ)
Description
The Intersil ACS573MS is a Radiation Hardened Octal Transparent
Latch with an active low output enable. The outputs are transparent to
the inputs when the latch enable (LE) is High. When the latch goes low
the data is latched. The output enable controls the three-state outputs.
When the output enable pins (OE) are high the output is in a high
impedance state. The latch operation is independent of the state of
output enable.
The ACS573MS utilizes advanced CMOS/SOS technology to achieve
high-speed operation. This device is a member of a radiation hardened,
high-speed, CMOS/SOS Logic family.
The ACS573MS is supplied in a 20 lead Ceramic Flatpack (K suffix) or a
Ordering Information
5962F9672401VRC
5962F9672401VXC
ACS573D/Sample
ACS573K/Sample
ACS573HMSR
SMD# 5962-96724 and Intersil’s QM Plan
(Typ)
- VIL = 30% of VCC Max
- VIH = 70% of VCC Min
PART NUMBER
1 A at VOL, VOH
TEMPERATURE RANGE
-55
-55
o
o
C to +125
C to +125
25
25
25
o
o
o
C
C
C
11
12
o
o
C
C
RAD (Si)/s, 20ns Pulse
RAD (Si)/s, 20ns Pulse
-10
MIL-PRF-38535 Class V
MIL-PRF-38535 Class V
Sample
Sample
Die
Errors/Bit/Day
o
C to +125
1
SCREENING LEVEL
2
/mg
o
C
ACS573MS
Pinouts
Three-State Transparent Latch
GND
OE
D0
D1
D2
D3
D4
D5
D6
D7
Radiation Hardened Octal
20 LEAD CERAMIC DUAL-IN-LINE
20 LEAD CERAMIC FLATPACK
GND
MIL-STD-1835 DESIGNATOR,
MIL-STD-1835 DESIGNATOR,
CDFP4-F20, LEAD FINISH C
CDIP2-T20, LEAD FINISH C
OE
D0
D1
D2
D3
D4
D5
D6
D7
10
1
2
3
4
5
6
7
8
9
20 Lead SBDIP
20 Lead Ceramic Flatpack
20 Lead SBDIP
20 Lead Ceramic Flatpack
Die
1
2
3
4
5
6
7
8
9
10
TOP VIEW
TOP VIEW
Spec Number
PACKAGE
File Number
20
19
18
17
16
15
14
13
12
11
18
17
16
15
14
13
12
20
19
11
VCC
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
LE
VCC
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
LE
518893
4093
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