ACS630D Intersil Corporation, ACS630D Datasheet

ACS630D

Manufacturer Part Number

ACS630D

Description

Radiation Hardened Edac ( Error Detection And Correction Circuit )

Manufacturer

Intersil Corporation

Datasheet

1.ACS630D.pdf (4 pages)

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January 1996

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

http://www.intersil.com or 407-727-9207

Features

• Devices QML Qualiﬁed in Accordance with MIL-PRF-38535

• Detailed Electrical and Screening Requirements are Contained in

• 1.25 Micron Radiation Hardened SOS CMOS

• Total Dose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >300K RAD (Si)

• Single Event Upset (SEU) Immunity: <1 x 10

• SEU LET Threshold . . . . . . . . . . . . . . . . . . . . . . . >100 MEV-cm

• Dose Rate Upset . . . . . . . . . . . . . . . . >10

• Dose Rate Survivability . . . . . . . . . . . >10

• Latch-Up Free Under Any Conditions

• Military Temperature Range . . . . . . . . . . . . . . . . . . -55

• Signiﬁcant Power Reduction Compared to ALSTTL Logic

• DC Operating Voltage Range . . . . . . . . . . . . . . . . . . . . 4.5V to 5.5V

• Input Logic Levels

• Input Current

• Fast Propagation Delay . . . . . . . . . . . . . . . . 37ns (Max), 24ns (Typ)

Description

The Intersil ACS630MS is a Radiation Hardened 16-bit parallel error

detection and correction circuit. It uses a modiﬁed Hamming code to

generate a 6-bit check word from each 16-bit data word. The check word

is stored with the data word during a memory write cycle; during a

memory read cycle a 22-bit word is taken form memory and checked for

errors. Single bit errors in the data words are ﬂagged and corrected.

Single bit errors in check words are ﬂagged but not corrected. The

position of the incorrect bit is pinpointed, in both cases, by the 6-bit error

syndrome code which is output during the error correction cycle.

The ACS630MS utilizes advanced CMOS/SOS technology to achieve

high-speed operation. This device is a member of a radiation hardened,

high-speed, CMOS/SOS Logic Family.

The ACS630MS is supplied in a 28 lead Ceramic Flatpack (K sufﬁx) or a

28 Lead Ceramic Dual-In-Line Package (D sufﬁx).

Ordering Information

5962F9671101VXC

5962F9671101VYC

ACS630D/Sample

ACS630K/Sample

ACS630HMSR

SMD# 5962-96711 and Intersil’ QM Plan

(Typ)

- VIL = 30% of VCC Max

- VIH = 70% of VCC Min

PART NUMBER

1 A at VOL, VOH

TEMPERATURE RANGE

-55

C to +125

Intersil Corporation 1999

RAD (Si)/s, 20ns Pulse

-10

MIL-PRF-38535 Class V

Sample

Die

Errors/Bit/Day

C to +125

(Error Detection and Correction Circuit)

SCREENING LEVEL

/mg

ACS630MS

Pinouts

DB10

DB11

GND

28 PIN CERAMIC DUAL-IN-LINE, MIL-STD-1835

DEF

DB0

DB1

DB2

DB3

DB4

DB5

DB6

DB7

DB8

DB9

28 PIN CERAMIC FLATPACK, MIL-STD-1835

DESIGNATOR CDFP3-F28, LEAD FINISH C

DESIGNATOR CDIP2-T28, LEAD FINISH C

Radiation Hardened EDAC

DB10

DB11

GND

DEF

DB0

DB1

DB2

DB3

DB4

DB5

DB6

DB7

DB8

DB9

28 Lead SBDIP

28 Lead Ceramic Flatpack

28 Lead SBDIP

28 Lead Ceramic Flatpack

Die

TOP VIEW

Spec Number

PACKAGE

File Number

VCC

SEF

CB0

CB1

CB2

CB3

CB4

CB5

DB15

DB14

DB13

DB12

518781

3199.1

VCC

SEF

CB0

CB1

CB2

CB3

CB4

CB5

DB15

DB14

DB13

DB12

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