ACS8515Rev2.1LC/P Semtech Corporation, ACS8515Rev2.1LC/P Datasheet - Page 17

• Manufacturer Part Number: ACS8515Rev2.1LC/P
• Description: Line Card Protection Switch For Sonet or SDH Network Elements
• Manufacturer: Semtech Corporation

Configuration Registers
Configuration Registers
Status Registers
Status Registers
Register Access
Register Access
Configuration Registers
Configuration Registers
Configuration Registers
Each configuration register reverts to a default
value on power-up or following a reset. Most
default values are fixed, but some will be pin-
settable. All configuration registers can be read
out over the microprocessor port.
Status Registers
Status Registers
Status Registers
The Status Registers contain readable registers.
They may all be read from outside the chip but
are not writable from outside the chip (except
for a clearing operation). All status registers
are read via shadow registers to avoid data
hits due to dynamic operation. Each individual
status register has a unique location.
Register Access
Register Access
Register Access
Most registers are of one of two types,
configuration registers or status registers, the
exceptions being the chip_revision register.
Configuration registers may be written to or read
from at any time (the complete 8-bit register
must be written, even if only one bit is being
modified). All status registers may be read at
any time and, in some status registers (such as
the sts_interrupts register), any individual data
field may be cleared by writing a ‘1’ into each
bit of the field (writing a ‘0’ value into a bit will
not affect the value of the bit). Details of each
register are given in the Register Map and
Register Map Description sections.
Revision 2.00/September 2003
ADVANCED COMMUNICATIONS
Semtech Corp.
17
Interrupt Enable and Clear
Interrupt Enable and Clear
Interrupt Enable and Clear
Interrupt Enable and Clear
Interrupt Enable and Clear
Interrupt requests are flagged on pin INTREQ
(active High).
Bits in the interrupt status register are set (high)
by the following conditions;
1. Any reference source becoming valid or going invalid
2. A change in the operating state (eg. Locked, Holdover
etc.)
3. A brief loss of the currently selected reference source
All interrupt sources are maskable via the mask
register cnfg_interrupt_mask, each one being
enabled by writing a '1' to the appropriate bit.
Any unmasked bit set in the interrupt status
register will cause the interrupt request pin to
be asserted (high).
All interrupts are cleared by writing a '1' to the
bit(s) to be cleared in the status register.
When all pending unmasked interrupts are
cleared the interrupt pin will go inactive (low).
The loss of the currently selected reference
source will eventually cause the input to be
considered invalid, triggering an interrupt. The
time taken to raise this interrupt is dependent
on the leaky bucket configuration of the activity
monitors. The very fastest leaky bucket setting
will still take up to 128 ms to trigger the
interrupt.
loss of the currently selected reference source
is provided to facilitate very fast source failure
detection if desired. It is triggered after missing
just a couple of cycles of the reference source.
ACS8515 Rev2.1 LC/P
The interrupt caused by the brief
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