ACS8526LC Semtech Corporation, ACS8526LC Datasheet - Page 13

• Manufacturer Part Number: ACS8526LC
• Description: Line Card Protection Switch for PDH, Sonet or SDH Systems
• Manufacturer: Semtech Corporation

frequencies are listed in Table 12, “APLL2 Frequencies,”
on page 24. Similarly to DPLL1, the output of the DPLL2
Forward DFS block is generated using DFS clocked by the
204.8 MHz system clock and will have an inherent jitter of
4.9 ns.
The DPLL2 feedback DFS also has the facility to be able
to use the post APLL2 (jitter-filtered) clock to generate the
feedback locking frequency. Again, this will give the
maximum performance by using a low jitter feedback.
APLL2 block is also for multiplying and filtering. The input
to APLL2 is controlled by MUX 2 (see “Multiplexers” on
page 13) and can come either from the DPLL2 Forward
DFS block or from DPLL1.
The frequency generated from the APLL2 is four times its
input frequency i.e. 311.04 MHz when used with a
77.76 MHz input. APLL2 is subsequently divided by 2, 4,
8, 12, 16, 48 and 64 and these are available at the O1
and 02 Outputs.
“Digital” Frequencies
DFS is also carried out by DPLL1 LF Output DFS block in
Figure 4 (E1/DS1 Synthesis block in Figure 1). This block
is clocked either by the DPLL1 77M Forward DFS block or
via the APLL1, and generates the single frequencies
Digital1 and Digital2 (see Table 13 and Table 14). The
input clock frequency of the DFS is always 77.76 MHz and
as such has a period of approximately 12 ns. The jitter
generated on the Digital outputs is relatively high,
because they do not pass through an APLL for jitter
filtering. The minimum level of jitter is when DPLL1 is in
analog feedback mode, when the p-p jitter will be
approximately 13 ns (equivalent to a period of the DFS
clock). The maximum jitter is generated when in digital
feedback mode, when the total is approximately 18 ns.
The E1/DS1 Synthesis block generates the E1/DS1 rates
for the APLLs, using the output from DPLL1. It generates
12E1, 16E1, 16DS1 or 24DS1, for selection by MUX1.
FrSync, MFrSync, 2 kHz and 8 kHz Clock Outputs
Whilst the FrSync and MFrSync Outputs are always
supplied from DPLL1, the 2 kHz and 8 kHz options
available from the O1 and O2 Outputs can be supplied
from either DPLL1 or DPLL2 (Reg. 7A Bit 7).
Multiplexers
Multiplexers MUX1 and MUX2 are used to select the
appropriate inputs to the Analog PLLs. The function they
Revision 4.01/June 2006 © Semtech Corp.
ADVANCED COMMUNICATIONS
FINAL
Page 13
represent is controlled by cnfg_DPLL1_frequency
Reg. 65.
APLL2 Input Selection using MUX 2
APLL1 Input Selection using MUX 1
Notes: (i) DPLL2 output cannot be selected for input to APLL1
APLLs
There are three main APLLs. APLL1 and APLL2 provide a
lower final output jitter reducing the 4.9 ns p-p jitter from
the digital down to 500 ps p-p and 60 ps RMS as typical
final outputs measured broadband (from 10 Hz to 1 GHz).
The feedback APLL (APLL3) is selected by default; it
provides improved performance over the digital feedback.
APLL Output Dividers
Each APLL has its own divider. Each divider
simultaneously outputs a series of fixed ratios of its APLL
input. Any of these divided outputs may be selected as the
output on Outputs O1 or O2 by configuring Reg. 61 and
Reg. 62, with the following exceptions: (APLL1)/2 and
(APLL1)/1 only available for Output 01 (differential port),
and (APLL1)/48 only available for Output 02.
DPLL2 selected for input to APLL2 (Reg. 65 Bit 6 = 0)
The input frequency is selected from the operating
frequency of DPLL2 (Reg. 64 Bits [2:0])
DPLL1 + LF Output DFS selected for Input to APLL2
DPLL1 (77.76 MHz) output fed to input of APLL1.
Analog feedback used in DPLL1 (Reg. 65 Bits [2:0] set
to 000)
DPLL1 (77.76 MHz) output fed to input of APLL1.
Digital feedback used in DPLL1 (Reg. 65 Bits [2:0] set
to 001)
DPLL1 + LF Output DFS selected for input to APLL1
• 12E1 (Reg. 65 Bit 6 = 1 and Bits [5:4] set to 00)
• 16E1 (Reg. 65 Bit 6 = 1 and Bits [5:4] set to 01)
• 24DS1 (Reg. 65 Bit 6 = 1 and Bits [5:4] set to 10)
• 16DS1 (Reg. 65 Bit 6 = 1 and Bits [5:4] set to 11)
• 12E1 (Reg. 65 Bits [2:0] set to 010)
• 16E1 (Reg. 65 Bits [2:0] set to 011)
• 24DS1 (Reg. 65 Bits [2:0] set to 100)
• 16DS1 (Reg. 65 Bits [2:0] set to 101)
(ii) If both multiplexers select LF Output DFS, the same
frequency value must be selected in Reg. 65 Bits
[2:0] and Reg. 65 Bits [5:4].
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