ACS8595 Semtech Corporation, ACS8595 Datasheet - Page 3

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ACS8595

Manufacturer Part Number
ACS8595
Description
Line Card Protection Switch for Sonet/sdh Advancedtca Systems
Manufacturer
Semtech Corporation
Datasheet

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Part Number
Manufacturer
Quantity
Price
Part Number:
ACS8595T
Manufacturer:
SEMTECH/美国升特
Quantity:
20 000
Table 3 Other Pins (cont...)
Revision 2.00/October 2005 © Semtech Corp.
ADVANCED COMMUNICATIONS
Pin No.
40,
41
42,
43
45
46
47
51
52
54
59
67
68
69
70
73
74
76
77
78
SEC1_POS,
SEC1_NEG
SEC2_POS,
SEC2_NEG
SYNC1
SEC1
SEC2
SYNC2
SEC3
SYNC3
TRST
TMS
CLKE
SDI
CSB
SCLK
PORB
TCK
TDO
TDI
Symbol
I/O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
PECL/LVDS Input Reference: Programmable, default
PECL/LVDS Input Reference: Programmable, default
TTL/CMOS
Type
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
D
D
D
D
D
D
D
D
D
D
U
D
U
D
D
19.44 MHz, PECL.
19.44 MHz PECL.
(Master) Multi-Frame Sync 2 kHz Input:
Connect to 2 or 8 kHz Multi-Frame Sync
output of Master SETS.
(Master) Input Reference: Programmable,
default 8 kHz.
(Slave) Input Reference: Programmable,
default 8 kHz.
(Slave) Multi-Frame Sync 2 kHz: Connect to
2 or 8 kHz Multi-Frame Sync output of Slave
SETS.
(Stand-by) Input Reference: External stand-
by reference clock source, programmable,
default 19.44 MHz.
(Stand-by) Input Reference: External stand-
by 2 or 8 kHz Multi-Frame Sync clock
source.
JTAG Control Reset Input: TRST = 1 to
enable JTAG Boundary Scan mode. TRST =
0 is Boundary Scan stand-by mode, still
allowing normal device operation (JTAG
logic transparent). NC if not used.
JTAG Test Mode Select: Boundary Scan
enable. Sampled on rising edge of TCK. NC
if not used.
SCLK Edge Select: SCLK active edge select,
CLKE = 1, selects falling edge of SCLK to be
active.
Serial Interface Address: Serial Data Input.
Chip Select (Active Low): This pin is
asserted Low by the microprocessor to
enable the microprocessor interface.
Serial Data Clock. When this pin goes High
data is latched from SDI pin.
Power-On Reset: Master reset. If PORB is
forced Low, all internal states are reset
back to default values.
JTAG Clock: Boundary Scan clock input.
JTAG Output: Serial test data output.
Updated on falling edge of TCK.
JTAG Input: Serial test data Input. Sampled
on rising edge of TCK.
Description
FINAL
Page 3
Table 3 Other Pins (cont...)
The ACS8595 ATCA is a Line Card Protection device
designed to complement the Semtech SETS devices
which maintain the SETS functions in both SONET and
SDH Network Elements. The ACS8595 ATCA extends this
functionality on to the Line Card, for which it has been
specifically designed. The ACS8595 ATCA uses “Hit-less”
group switching between Master and Slave inputs or a
third (Stand-by) input group, to generate and maintain
accurate and stable SEC and frame synchronization pulse
outputs for distribution on the Line Card, typically for
Advanced Mezzaninie Cards (AMCs) on AdvancedTCA
equipment.
The ACS8595 provides a simple, compact, yet flexible
solution, which can be easily tailored for use with a range
of transmission formats and rates, via software
configuration.
The ACS8595 employs various mechanisms to maintain
the integrity of its output clocks when its input clocks fail
or fall below the required specification levels. By
smoothing out the effects of these input anomalies, the
ACS8595 improves the overall stability and reliability of
Introduction
Pin No.
83
88
89
90
93
94
100
SDO
O3
O4
O2
O5
O6
SONSDHB
Symbol
I/O
O
O
O
O
O
O
I
TTL/CMOS
TTL/CMOS
TTL/CMOS
TTL/CMOS
TTL/CMOS
Type
TTL
TTL
D
D
ACS8595 ATCA
Interface Address: SPI compatible Serial
Data Output.
Output Reference: Programmable, disabled
by default.
Output Reference: Programmable, disabled
by default.
Output Reference: Programmable, default
19.44 MHz.
Output Reference: Programmable, disabled
by default.
Output Reference: Programmable, disabled
by default.
SONET or SDH Frequency Select: Sets the
initial power-up state (or state after a
PORB) of the SONET/SDH frequency
selection registers, Reg. 34, Bit 2 and
Reg. 38, Bit 5, Bit 6 and Reg. 64 Bit 4.
When set Low, SDH rates are selected
(2.048 MHz etc.) and when set High,
SONET rates are selected (1.544 MHz etc.)
The register states can be changed after
power-up by software.
PRODUCT BRIEF
Description
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