ACS8522A Semtech Corporation, ACS8522A Datasheet

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ACS8522A

Manufacturer Part Number
ACS8522A
Description
Synchronous Equipment Timing Source for Stratum 3/4e/4 and SMC Systems
Manufacturer
Semtech Corporation
Datasheet

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Part Number:
ACS8522A
Manufacturer:
SEMTECH/美国升特
Quantity:
20 000
The ACS8522 is a highly integrated, single-chip solution
for the Synchronous Equipment Timing Source (SETS)
function in a SONET or SDH Network Element. The device
generates SONET or SDH Equipment Clocks (SEC) and
Frame Synchronization clocks. The ACS8522 is fully
compliant with the required international specifications
and standards.
The device supports Free-run, Locked and Holdover
modes, with mode selection controlled either
automatically by an internal state machine or forced by
register configuration.
The ACS8522 accepts up to four independent input SEC
reference clock sources from Recovered Line Clock, PDH
network, and Node Synchronization. The ACS8522
generates independent SEC and BITS clocks, an 8 kHz
Frame Synchronization clock and a 2 kHz Multi-Frame
Synchronization clock, both with programmable pulse
width and polarity.
The ACS8522 includes a Serial Port, which can be SPI
compatible, providing access to the configuration and
status registers for device setup.
The ACS8522 supports IEEE 1149.1
scan.
The User can choose between OCXO or TCXO to define the
Stratum and/or Holdover performance required.
Figure 1 Block Diagram of the ACS8522 SETS LITE
Revision 5/November 2006 © Semtech Corp.
Description
ADVANCED COMMUNICATIONS
Block Diagram
Inputs: 4 x TTL
Programmable;
2 kHz
4 kHz
N x 8 kHz
1.544/2.048 MHz
6.48 MHz
19.44 MHz
25.92 MHz
38.88 MHz
51.84 MHz
77.76 MHz
ADVANCED COMMUNICATIONS
TRST
TMS
TDO
TCK
TDI
Selection
Monitors
1149.1
4 x SEC
Control
JTAG
IEEE
Input
and
Port
Generator
OCXO or
T4 DPLL
Selector
T0 DPLL
Selector
Clock
TCXO
Chip
Divider, 1/n
Divider, 1/n
n = 1 to 2
n = 1 to 2
Priority
T4 DPLL/Freq. Synthesis
T0 DPLL/Freq. Synthesis
[5]
Optional
Optional
Table
JTAG boundary
Register Set
14
14
PFD
PFD
Digital
Digital
FINAL
FINAL
Filter
Filter
Loop
Loop
Page 1
Serial
Port
Features
Synchronous Equipment Timing Source for
DTO
DTO
Suitable for Stratum 3, 4E, 4 and SONET Minimum
Clock (SMC) or SONET/SDH Equipment Clock (SEC)
applications (to Telcordia 1244-CORE
and GR-253
specifications)
Accepts four individual input reference clocks, all with
robust input clock source quality monitoring
Simultaneously generates four output clocks, plus two
Sync pulse outputs
Absolute Holdover accuracy better than 3 x 10
(manual), 7.5 x 10
stability defined by choice of external XO
Programmable PLL bandwidth, for wander and jitter
tracking/attenuation, 0.1 Hz to 70 Hz in 10 steps
Automatic hit-less source switchover on loss of input
Serial SPI compatible interface
Output phase adjustment in 6 ps steps up to ±200 ns
IEEE 1149.1
Available in LQFP 64-pin package
Single 3.3 V operation. 5 V tolerant
Lead (Pb)-free version available (ACS8522T), RoHS
and WEEE compliant.
Stratum 3/4E/4 and SMC Systems
T0 Feedback
Frequency
Frequency
T0 Output
T4 Output
[17]
Dividers
Dividers
[5]
APLL
APLL
APLL
, and ITU-T G.813
JTAG Boundary Scan
ACS8522 SETS LITE
-14
(instantaneous); Holdover
Output
Ports
FrSync
MFrSync
O1
to
O4
&
F8522P_001BLOCKDIA_04
[11]
Output O1: PECL/LVDS
Outputs O2 - 04: TTL
Programmable;
E1/DS1 (2.048/
1.544 MHz)
and frequency
multiples:
1.5 x, 2 x, 3 x
4 x, 6 x, 12 x
16 x and 24 x
E3/DS3
2 kHz
8 kHz
and OC-N* rates
8 kHz
(FrSync)
2 kHz
(MFrSync)
OC-N* rates =
OC-1 51.84 MHz
OC-3 155.52 MHz
and derivatives:
6.48 MHz
19.44 MHz
25.92 MHz
38.88 MHz
51.84 MHz
77.76 MHz
155.52 MHz
311.04 MHz
Options Ι and ΙΙ
[19]
DATASHEET
www.semtech.com
Stratum 3
-10

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