S1A0903X01-Q0R0 Samsung Electronics, S1A0903X01-Q0R0 Datasheet - Page 26

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S1A0903X01-Q0R0

Manufacturer Part Number
S1A0903X01-Q0R0
Description
AM/FM 1 Chip Tuner with PLL
Manufacturer
Samsung Electronics
Datasheet
S1A0903X01
PHASE FREQUENCY DETECTOR
States are changed on rising edges of Fr or Fc in Figure. 9(Fr moving to higher states and Fc moving to lower
states) Suppose the circuit is initially in state 1, Then alternate rising edges on Fr and Fc will cycle between
states 1 and 2. If Fc is constantly falling behind Fr in phase, as in the timing diagram(Figure. 11 A point), then
eventually there will be two Fr rising edges without an intervening Fc rising edge. This will take the circuit to state
3, and thereafter it will cycle between state 2 and state3.
remains in state 2 almost all the time
26
For phase difference of Fc and Fr is almost zero, the rising edges of Fr and Fc are coincident, and the PD
Z-state Phase Frequency Detector is composed of 3-State PFD and two MOS gates
State 1 : make the frequency of Fc slower.
State 2 : hold the frequency of Fc.
State 3 : make the frequency of Fc faster.
State transition at rising edges of Fr and Fc
rising edge of Fr : cause current state to go high
rising edge of Fc : cause current state to go low
FC
FR
FC
STATE1
B=V
A=V
H
L
Figure 9. PFD state diagram
Figure 10. PFD scheme
FR
FC
STATE2
A=V
B=V
L
L
B
A
FR
FC
a
b
b
a
STATE3
A=V
B=V
c
d
e
e
d
c
f
f
H
L
VSSA
VDD
AM/FM 1CHIP TUNER WITH PLL
PD
FR

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