LM2501 National Semiconductor, LM2501 Datasheet
LM2501
Manufacturer Part Number
LM2501
Description
Mobile Pixel Link (MPL) Camera Interface Serializer and Deserializer
Manufacturer
National Semiconductor
Datasheet
1.LM2501.pdf
(14 pages)
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© 2004 National Semiconductor Corporation
Ordering Information
LM2501
Mobile Pixel Link (MPL) Camera Interface Serializer and
Deserializer
General Description
The LM2501 device is a Serializer/Deserializer that adapts
existing video busses to Mobile Pixel Link (MPL). MPL is
intended to replace wide LVCMOS video interfaces inside
portable electronics equipment benefiting their cost, size,
EMI and power consumption.
By using the LM2501 SERDES chipset, the interconnect is
reduced from 12 active signals to only 3 active signals
providing a 75% reduction. This eases interconect and flex
design, size and cost.
Contained in a 24 lead Ultra Thin CSP Package, the Serial-
izer resides beside the video source (camera) and translates
the parallel bus from LVCMOS levels to serial MPL levels for
transmission over a flex cable to the Deserializer located by
the respective destination Video Input Port.
An extra clock transport is provided to deliver a clock signal
to the target. For example, from the main board to the flip
board where the camera module is located. Transmission of
the clock also benefits from MPL’s low power transmission
and low EMI.
The Power_Down (PD*) input controls the power state of the
MPL interface. When PD* is asserted, the MD, MC and WC
signals are powered down to save current and reduce power
dissipation.
Typical Application Diagram
I2C
®
is a registered trademark of Phillips Corporation.
LM2501SL
NSID
24-Lead Ultra Thin CSP 3.5 X 4.5 X 0.6 mm
DS200916
Package Type
Features
n 160 Mbps Raw Throughput
n MPL-0 Meets MPL Physical Layer Specification
n Configurable as a Serializer or Deserializer
n Complete LVCMOS to MPL Translation
n Serializes 8-bit Camera Interface
n Link power down mode reduces quiescent power under
n 1.7V–3.1V and 2.9-3.1V Supply Voltage
n Interfaces to 1.8V–3.0V Logic
n Offered in a small 24L UCSP Package
System Benefits
n Reduced Wire Interface
n Low Power
n Low EMI
n Extra Clock Transport
n Intrinsic Level Translation
— 8-bit color data
— plus VSYNC and HSYNC bits
∼ 10 µA (actual TBD)
— 3.5 mm X 4.5 mm
— 0.6 mm Max Height
ADVANCE INFORMATION
Package ID
SLE24A
20091601
www.national.com
June 2004
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