MAX1270ACAI Maxim, MAX1270ACAI Datasheet - Page 8

• Manufacturer Part Number: MAX1270ACAI
• Description: Multirange / +5V / 8-Channel / Serial 12-Bit ADCs
• Manufacturer: Maxim

Multirange, +5V, 8-Channel,
Serial 12-Bit ADCs
Figure 1. Reference-Adjust Circuit
The MAX1270/MAX1271 multirange, fault-tolerant ADCs
use successive approximation and internal track/hold
(T/H) circuitry to convert an analog signal to a 12-bit
digital output. Figure 3 shows the block diagram of the
MAX1270/MAX1271.
The T/H enters tracking/acquisition mode on the falling
edge of the sixth clock in the 8-bit input control word,
and enters hold/conversion mode when the timed
acquisition interval (six clock cycles, 3µs minimum)
ends. In internal clock mode, the acquisition is timed by
two external clock cycles and four internal clock cycles.
When operating in bipolar (MAX1270 and MAX1271) or
Figure 3. Block Diagram
7-176
100k
24k
REFADJ
___________________________________________________________________________________
+5V
SHDN
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
REF
510k
0.01µF
Detailed Description
Analog-Input Track/Hold
REFERENCE
CONDITIONING
AND SIGNAL
2.5V
ANALOG
INPUT
MUX
Converter Operation
REFADJ
MAX1270
MAX1271
10k
1.638
Av =
DIN
SERIAL INTERFACE LOGIC
T/H
+4.096V
SSTRB
unipolar mode (MAX1270) the signal applied at the
input channel is rescaled through the resistor-divider
network formed by R1, R2, and R3 (Figure 4); a low-
impedance (<4Ω) input source is recommended to
minimize gain error. When the MAX1271 is configured
for unipolar mode, the channel input resistance (R
becomes a fixed 5.12kΩ (typ). Source impedances
below 15kΩ (0 to V
significantly affect the AC performance of the ADC.
The acquisition time (t
output resistance, the channel input resistance, and the
T/H capacitance. Higher source impedances can be
used if an input capacitor is connected between the
analog inputs and AGND. Note that the input capacitor
forms an RC filter with the input source impedance, lim-
iting the ADC’s signal bandwidth.
Figure 2. Output Load Circuit for Timing Characteristics
DOUT
SSTRB
DOUT
OR
a) HIGH-Z TO V
0.5mA
AND V
CS
IN
REF
OUT
OH
OH
TO HIGH-Z
, V
12-BIT SAR ADC
OL
REF
MAX1270
MAX1271
TO V
ACQ
C
) and 5kΩ (0 to V
LOAD
OH
,
) is a function of the source
SCLK
CLOCK
b) HIGH-Z TO V
CLOCK
INT
SSTRB
DOUT
OR
AND V
5mA
OH
REF
OH
+5V
TO HIGH-Z
, V
OL
/2) do not
C
LOAD
V
AGND
DGND
TO V
DD
OH
,
IN
)