MAX1492 Maxim, MAX1492 Datasheet - Page 8

• Manufacturer Part Number: MAX1492
• Description: 3.5- and 4.5-Digit / Single-Chip ADCs with LCD Drivers
• Manufacturer: Maxim

3.5- and 4.5-Digit, Single-Chip ADCs
with LCD Drivers
8
MAX1492
_______________________________________________________________________________________
10
11
12
13
14
15
16
17
18
19
20
21
22
23
1
2
3
4
5
6
7
8
9
PIN
MAX1494
30
31
32
10
11
12
13
14
15
16
17
18
19
20
1
2
3
4
5
6
7
8
9
LOWBATT
NAME
DOUT
DV
AV
REF+
SCLK
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
GND
AIN+
REF-
EOC
CLK
AIN-
DIN
CS
DD
DD
External Clock Input. When the EXTCLK bit in the control register is set, CLK is the
master clock input for the modulator and the filter (frequency = 4.9152MHz). When the
EXTCLK bit in the control register is reset, the internal clock is used. Connect CLK to
GND or DV
Digital Power Input. Connect DV
GND with 0.1µF and 4.7µF capacitors.
Ground
Analog Power Input. Connect AV
GND with 0.1µF and 4.7µF capacitors.
Positive Analog Input. Positive side of fully differential analog input. Bypass AIN+ to
GND with a 0.1µF or greater capacitor.
Negative Analog Input. Negative side of fully differential analog input. Bypass AIN- to
GND with a 0.1µF or greater capacitor.
Negative Reference Input. During internal reference operation, connect REF- to GND.
For external reference operation, bypass REF- to GND with a 0.1µF capacitor and set
V
Positive Reference Input. During internal reference operation, connect a 4.7µF capacitor
from REF+ to GND. For external reference operation, bypass REF+ to GND with a 0.1µF
capacitor and set V
Low-Battery Input. When V
on and the LOWBATT bit latches high in the status register.
Active-Low, End-of-Conversion Logic Output. A logic-low at EOC indicates that a new
ADC result is available in the ADC result register.
Active-Low Chip-Select Input. Forcing CS low activates the serial interface.
Serial Data Input. Data present at DIN is shifted into the internal registers in response to
a rising edge at SCLK when CS is low.
Serial Clock Input. Apply an external clock to SCLK to facilitate communication through
the serial bus. SCLK can idle high or low.
Serial Data Output. DOUT presents serial data in response to register queries. Data
shifts out on the falling edge of SCLK. DOUT goes high impedance when CS is high.
LCD Segment 1 Driver
LCD Segment 2 Driver
LCD Segment 3 Driver
LCD Segment 4 Driver
LCD Segment 5 Driver
LCD Segment 6 Driver
LCD Segment 7 Driver
LCD Segment 8 Driver
LCD Segment 9 Driver
REF-
from -2.2V to +2.2V, provided V
DD
when the internal oscillator is used.
REF+
from -2.2V to +2.2V, provided V
LOWBATT
DD
DD
to a 2.7V to 5.25V power supply. Bypass DV
to a 2.7V to 5.25V power supply. Bypass AV
< 2.048V (typ), the LOWBATT symbol on LCD turns
REF+
FUNCTION
> V
REF-
.
REF+
Pin Description
> V
REF-
.
DD
DD
to
to