MAX17499 Maxim Integrated Products, MAX17499 Datasheet - Page 10

• Manufacturer Part Number: MAX17499
• Description: (MAX17499 / MAX17500) Current-Mode PWM Controllers
• Manufacturer: Maxim Integrated Products

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For the MAX17500, the voltage at IN is normally derived
from a tertiary winding of the transformer. However, at
startup there is no energy being delivered through the
transformer; hence, a special bootstrap sequence is
required. Figure 2 shows the voltages at V
during startup. Initially, both V
the line voltage is applied, C1 charges through the
startup resistor, R1, to an intermediate voltage. At this
Current-Mode PWM Controllers with
Programmable Switching Frequency
Figure 2. V
MAX17500 in Bootstrapped Mode (Figure 1)
Figure 3. UVLO/EN and UFLG Operation Timing
10
______________________________________________________________________________________
IN
and V
CC
V
V
V
UVLO/EN
NDRV
UFLG
During Startup When Using the
100ms/div
SHUTDOWN
IN
LOW
(±1%)
1.23V
MAX17499/MAX17500 fig02
and V
CC
3μs
t
V
2V/div
V
5V/div
0V
3ms
EXTR
are 0V. After
CC
IN
HIGH-Z
IN
and V
CC
NDRV SWITCHING
point, the internal regulator begins charging C2 (see
Figure 1). Only 50μA of the current supplied through R1
is used by the MAX17500; the remaining input current
charges C1 and C2. The charging of C2 stops when
the V
voltage across C1 continues rising until it reaches the
wake-up level of 21.6V. Once V
strap UVLO threshold, NDRV begins switching the
MOSFET and transfers energy to the secondary and
tertiary outputs. If the voltage on the tertiary output
builds to higher than 9.74V (the bootstrap UVLO lower
threshold), then startup has been accomplished and
sustained operation commences. If V
9.74V before startup is complete, the device goes back
to low-current UVLO. In this case, increase the value of
C1 to store enough energy to allow for the voltage at
the tertiary winding to build up.
The devices have an open-drain undervoltage flag out-
put (UFLG). When used with an optocoupler, the UFLG
output can serve to sequence a secondary-side con-
troller. An internal 210μs delay occurs the instant the
voltage on UVLO/EN drops below 1.17V until NDRV
stops switching. This allows for the UFLG output to
change state before the devices shut down (Figure 3).
When the voltage at the UVLO/EN is above the thresh-
old, UFLG is high impedance. When UVLO/EN is below
the threshold, UFLG goes low. UFLG is not affected by
bootstrap UVLO (MAX17500).
0.6μs
CC
voltage reaches approximately 9.5V, while the
210μs
1.17V (typ)
t
EXTF
LOW
SHUTDOWN
UVLO Flag (UFLG)
IN
exceeds the boot-
IN
drops below
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