MAX1771 Maxim, MAX1771 Datasheet - Page 13

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MAX1771

Manufacturer Part Number
MAX1771
Description
12V or Adjustable / High-Efficiency / Low IQ / Step-Up DC-DC Controller
Manufacturer
Maxim
Datasheet

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DataSheet4U.com
www.DataSheet4U.com
DataSheet
4
U
.com
When using a power supply that decays with time
(such as a battery), the N-FET transistor will operate in
its linear region when the voltage at EXT approaches
the threshold voltage of the FET, dissipating excessive
power. Prolonged operation in this mode may damage
the FET. This effect is much more significant in non-
bootstrapped mode than in bootstrapped mode, since
bootstrapped mode typically provides much higher
V
is above the V
(such as the MAX8211) to put the IC in shutdown mode
once the input supply voltage falls below a predeter-
mined minimum value. Excessive loads with low input
voltages can also cause this condition.
The Typical Operating Characteristics show the Start-
Up Voltage vs. Load Current graph for bootstrapped-
mode operation. This graph depends on the type
of power switch used. The MAX1771 is not designed to
start up under full load in bootstrapped mode with low
input voltages.
Figure 5. Step-Up/Down for a 5V/3.3V Output
__________Applications Information
GS
3V = OFF
SEE TEXT FOR FURTHER COMPONENT INFO
**V
**REQUIRED TO START UNDER FULL LOAD
**MOTOROLA MMFT3055ELT1
† FOR 5V: R2 = 200k , R3 = 470k
0.1 F
voltages. To avoid this condition, make sure V
IN
C4
MAY BE LOWER THAN INDICATED IF THE SUPPLY IS NOT
3.3V: R2 = 100k , R3 = 20k
5
4
SHDN
REF
GND
7
MAX1771
TH
AGND
R2 †
2.2 F
6
of the FET, or use a voltage detector
Low Input Voltage Operation
______________________________________________________________________________________
C1
V+
EXT
FB
CS
2
3
1
8
Starting Up Under Load
R3 †
47pF
C5
D2
1N5817
3V TO 11V
V
Q1**
IN
12V or Adjustable, High-Efficiency,
*
L1
20 H
1 CTX20-4
R1
0.1
Low I
47 F
16V
C2
L2
1N5817
D1
DataSheet4U.com
Q
V
5V
500mA
C3
220 F
10V
OUT
, Step-Up DC-DC Controller
EXT
Due to high current levels and fast switching wave-
forms, which radiate noise, proper PC board layout is
essential. Protect sensitive analog grounds by using a
star ground configuration. Minimize ground noise by
connecting GND, the input bypass capacitor ground
lead, and the output filter capacitor ground lead to a
single point (star ground configuration). Also, minimize
lead lengths to reduce stray capacitance, trace resis-
tance, and radiated noise. Place input bypass capaci-
tor C2 as close as possible to V+ and GND.
Excessive noise at the V+ input may falsely trigger the
timing circuitry, resulting in short pulses at EXT. If this
occurs it will have a negligible effect on circuit efficien-
cy. If desired, place a 4.7µF directly across the V+ and
GND pins (in parallel with the 0.1µF C2 bypass capaci-
tor) to reduce the noise at V+.
The circuit shown in Figure 5 generates 5V (or 3.3V) at
500mA with 85% efficiency, from an input voltage that
varies above and below the output. The output couples
to the switching circuitry via a capacitor. This configu-
ration offers two advantages over flyback-transformer
and step-up linear-regulator circuits: smooth regulation
as the input passes through the output, and no output
current in shutdown.
This circuit requires two inductors, which can be wound
on one core with no regard to coupling since they do
not work as a transformer. L1 and L2 can either be
wound together (as with the Coiltronics CTX20-4) or
kept as two separate inductors; both methods provide
equal performance. Capacitors C2 and C3 should be
low-ESR types for best efficiency. A 1µF ceramic
capacitor will work at C2, but with about 3% efficiency
loss. C2’s voltage rating must be greater than the maxi-
mum input voltage. Also note that the LX switch must
withstand a voltage equal to the sum of the input and
output voltage; for example, when converting 11V to
5V, the switch must withstand 16V.
LX switch pulses are captured by Schottky diode D2 to
boost V+ to (V
a low input voltage, but also limits the maximum input
supply to 11V. If the input voltage does not fall below 4V
and if a 3V logic threshold FET is used for Q1, you may
omit D2 and connect V+ directly to the input supply.
The circuit in Figure 6 generates 12V from a 4.5V to
16V input. Higher input voltages are possible if you
4 Cells to 5V (or 3 Cells to 3.3V), 500mA
OUT
+ V
Other Application Circuits
IN
). This improves efficiency with
Layout Considerations
Step-Up/Down Converter
12V Output Buck/Boost
13

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