MAX3634 Maxim Integrated Products, MAX3634 Datasheet - Page 5

• Manufacturer Part Number: MAX3634
• Description: 622Mbps/1244Mbps Burst-Mode Clock Phase Aligner
• Manufacturer: Maxim Integrated Products

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The MAX3634 CPA provides serial clock and data out-
puts for GPON upstream bursts.
The burst-mode CPA operates on the principle that the
recovered clock from the ONT CDR is used at each
ONT to clock upstream data bursts out of the ONT con-
troller. The burst-mode CPA has logic that determines
the correct phase relationship between the upstream
data and the OLT reference clock at the beginning of
each ONT’s burst, and resamples the upstream data at
each bit using that clock.
The burst-mode CPA contains a phase-locked loop
(PLL) that synchronizes its oscillator to the reference
clock input. This oscillator drives a phase splitter, which
generates eight evenly spaced phases of the serial
clock, which are used to sample the input data at 1/8th
bit intervals in eight flip-flops. Combinatorial and
sequential logic measures the preamble, and based on
the phase of the preamble, determines which one of
the eight clock phases is at the center of the input data
bits. The data from the flip-flop associated with this
phase is then steered through a multiplexer to the CPA
output, which requires four or five additional clock peri-
ods until valid data is output. The CPA serial output
Figure 2. Functional Block Diagram
622Mbps/1244Mbps Burst-Mode Clock Phase
REFCLK+
REFCLK-
RATESEL
_______________________________________________________________________________________
RST+
RST-
SDI+
SDI-
General Description
LVPECL
LVPECL
LVPECL
TTL
Theory of Operation
Aligner for GPON OLT Applications
PLL/PHASE SPLITTER
φ0
622Mbps/1244Mbps
φ7
PHASE-ACQUISITION LOGIC
D
D
D
Q
Q
Q
clock is continuous, without any phase jumps or dis-
continuities from burst to burst.
The burst-mode CPA requires a preamble sequence of
1010101010101 (13 bits) for correct phase alignment.
Typically, output begins after the 12th bit, although for
certain data/phase relationships, 13 bits are required.
An LVPECL-compatible lock status output is provided,
which indicates when the correct phase has been
acquired and valid serial output data is available. This
output remains low until reset by the burst reset input
(RST). The output data is disabled (held low) during the
period between reset and lock.
The MAX3634 includes a PLL, which multiplies the ref-
erence clock by eight for use in the retiming circuitry.
For correct operation, the REFCLK input must be con-
nected to the OLT byte-rate reference clock, which
must be equal to 1/8th the serial data rate, and must
have a 40% to 60% duty cycle. This must be the same
clock source used to time the downstream data, and
the upstream data must be frequency locked to this
source.
The RATESEL input is used to configure 622Mbps or
1244Mbps operation; when RATESEL is high, the
MAX3634 operates at 622Mbps.
MUX
BURST-MODE CPA
MAX3634
LVPECL
LVPECL
LVPECL
Reference Clock Input
SCLK+
LOCK+
SCLK-
LOCK-
SDO+
SDO-
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