WM8146 Wolfson Microelectronics Ltd., WM8146 Datasheet - Page 9

• Manufacturer Part Number: WM8146
• Description: 12-bit ( 8+4-bit ) Linear Sensor Image Processor
• Manufacturer: Wolfson Microelectronics Ltd.

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OFFSET ADJUST AND PROGRAMMABLE GAIN
WOLFSON MICROELECTRONICS LTD
The output from the CDS block is a differential signal, which is amplified by a 5-bit PGA then added
to the output of an 8-bit (+sign) offset DAC to compensate for sensor d.c. offsets. The gain and offset
for each channel are independently programmable by writing to control bits DAC[7:0] and PGA[4:0].
The following diagram shows the signal path through the device.
Figure 8 Signal Flow Diagram
The following equations enable the user to calculate the settings required for the PGAs and offset
DACs.
INPUT SAMPLING AND REFERENCING
If CDS=1, the previously sampled reset level, V
(i.e. CDS operation).
V
If CDS=0, the simultaneously sampled V
GAIN ADJUST
The signal is then multiplied by the PGA gain, approximately 0.5 to 8.25 in 32 equal gain steps.
OFFSET (BLACK-LEVEL) ADJUST
The resultant signal is added to the Offset DAC output which has a range of VMID/2 (or 1.5*VMID/2 if
the DACRNG bit is set).
V
ANALOGUE TO DIGITAL CONVERSION
The analogue signal is then converted to a 12-bit unsigned number. This is equivalent to a
multiplication by 4096/(V
At this stage, the input to the ADC should be between -1V and +1V, so D
-2047 and +2048. If the input is over-range, it will be clipped to within the range (-2047,2048).
2047 is added to the ADC output, to give code 2047 for zero input signal to the ADC. This is
equivalent to the +VMID shown in the block diagram on page 1.
V
V
D
1
3
1
2
1
= V
= V
= V
= V
= V
== INT{ (V
= V
V
V
V
MID
IN
RESET
2
IN
2
IN
1
1
+ [(1-2*DSIGN) * DAC_CODE/255 * (VMID/2 + VMID/4 * DACRNG)]
+ V
* G
- V
* (0.5+(PGA[4:0]*0.25))
- V
C D S = 0
C D S = 1
RESET
DAC
MID
3
/V
(1-2*DSIGN)*(DAC[7:0]/255)*(V
SAMPLING
BLOCK
FS
INPUT
+
) * 4096 } + 2047
A = 0.5+(PGA[4:0]*0.25)
-
V
FS
1
P G A g a i n
), where V
BLOCK
PGA
X
V
2
OFFSET DAC
+ +
FS
BLOCK
Offset
D A C
MID
= 2V .
/2 + V
MID
V
3
a n a l o g
MID
is subtracted instead (i.e. non-CDS operation).
/ 4 * D A C R N G )
RESET
V
3
, is subtracted from the input video signal V
x (4096/V
ADC BLOCK
F S
V
V
V
C D S , D A C [ 7 : 0 ] , D S I G N , D A C R N G , P G A [ 4 : 0 ]
and INVOP are set by programming internal
control registers.
C D S = 1 f o r C D S , 0 f o r n o n - C D S
) + 2 0 4 7
IN
R E S E T
MID
is RINP or GINP or BINP
is AVDD/2
is V
IN
D
digital
D2 = D1 if INVOP = 0
D 2 = 4 0 9 5 - D 1 i f I N V O P = 1
sampled during reset clamp
1
1
OUTPUT
INVERT
BLOCK
[11:0] should lie between
PP Rev 1.1 January 2000
FOR 8-BIT OUTPUT
TO MULTIPLEXER
D
2
WM8146
IN
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