ADC71JG Burr-Brown Corporation, ADC71JG Datasheet - Page 6

• Manufacturer Part Number: ADC71JG
• Description: 16-bit Analog-to-digital Converter
• Manufacturer: Burr-Brown Corporation

FIGURE 5. ADC71 Connections for: 10V Analog Input, 14-Bit Resolution (Short-Cycled), Parallel Data Output.
SERIAL DATA
Two straight binary (complementary) codes are available on
the serial output line: CSB and COB. The serial data is
available only during conversion and appears with MSB
occurring first. The serial data is synchronous with the
internal clock as shown in the timing diagrams of Figures 2
and 3. The LSB and transition values shown in Table I also
apply to the serial data output except for the CTC code.
DISCUSSION
OF SPECIFICATIONS
The ADC71 is specified to provide critical performance
criteria for a wide variety of applications. The most critical
specifications for an A/D converter are linearity, drift, gain
and offset errors. This ADC is factory-trimmed and tested
for all critical key specifications.
GAIN AND OFFSET ERROR
Initial Gain and Offset errors are factory-trimmed to typi-
cally 0.1% of FSR (typically 0.05% for unipolar offset) at
25 C. These errors may be trimmed to zero by connecting
external trim potentiometers as shown in Figures 6 and 7.
POWER SUPPLY SENSITIVITY
Changes in the DC power supplies will affect accuracy. The
power supply sensitivity is specified for 0.003% of FSR/
% V
supplies. Normally, regulated power supplies with 1% or
less ripple are recommended for use with this ADC. See
Layout Precautions, Power Supply Decoupling and Figure
8.
MSB
NC
S
for 15V supplies and 0.001% of FSR/%
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9
®
ADC71
ADC71
Dotted Lines
Are External
Connections
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
NC
NC
Bipolar
Offset
0.01µF
270k
1.8M
S
for +5
(1)
NOTE: (1) Capacitor should be connected even if external gain adjust is not used.
Convert Command From
Control Logic
Status Output to
Control Logic
6
Adjust
Gain
FIGURE 6. Two Methods of Connecting Optional Offset
FIGURE 7. Connecting Optional Gain Adjust with a 0.2%
Analog Common
(a)
Comparator In
(b)
Comparator In
Gain Adjust
10k to
100k
29
22
27
27
180k
Adjust with a 0.4% of FSR of Adjustment.
Range of Adjustment.
+
1µF
0.01µF
Adjust
Offset
22k
270k
Common
1.8M
180k
Digital
10k to
100k
+
+
1µF
1µF
Common
Analog
+15VDC
–15VDC
+15VDC
–15VDC
+15VDC
–15VDC
10k to 100k
Gain Adjust
10k to 100k
Offset Adjust
10k to 100k
Offset Adjust
–15VDC
+15VDC
+5VDC
Analog Input
±10V