ADS8320E Burr-Brown Corporation, ADS8320E Datasheet - Page 10

• Manufacturer Part Number: ADS8320E
• Description: 16-Bit/ High-Speed/ 2.7V to 5V microPower Sampling ANALOG-TO-DIGITAL CONVERTER
• Manufacturer: Burr-Brown Corporation

FIGURE 3. ADS8320 Basic Timing Diagrams.
SERIAL INTERFACE
The ADS8320 communicates with microprocessors and other
digital systems via a synchronous 3-wire serial interface as
shown in Figure 3 and Table I. The DCLOCK signal syn-
chronizes the data transfer with each bit being transmitted on
the falling edge of DCLOCK. Most receiving systems will
capture the bitstream on the rising edge of DCLOCK. How-
ever, if the minimum hold time for D
system can use the falling edge of DCLOCK to capture each
bit.
A falling CS signal initiates the conversion and data transfer.
The first 4.5 to 5.0 clock periods of the conversion cycle are
used to sample the input signal. After the fifth falling
DCLOCK edge, D
value for one clock period. For the next 16 DCLOCK
periods, D
cant bit first. After the least significant bit (B0) has been
output, subsequent clocks will repeat the output data but in
a least significant bit first format.
After the most significant bit (B15) has been repeated, D
will tri-state. Subsequent clocks will have no effect on the
converter. A new conversion is initiated only when CS has
been taken HIGH and returned LOW.
TABLE I. Timing Specifications (V
SYMBOL
t
t
t
t
t
t
t
t
t
t
t
SMPL
CONV
CYC
CSD
SUCS
hDO
dDO
dis
en
f
r
CS/SHDN
DCLOCK
CS Rising to D
OUT
Analog Input Sample Time
DCLOCK Falling to D
DCLOCK Falling to Next
–40 C to +85 C.
Current D
D
DCLOCK Falling to
®
OUT
Conversion Time
will output the conversion result, most signifi-
Throughput Rate
DCLOCK Rising
D
DESCRIPTION
DCLOCK LOW
D
CS Falling to
CS Falling to
OUT
ADS8320
OUT
D
Enabled
OUT
Rise Time
OUT
OUT
Fall Time
Valid
OUT
Not Valid
is enabled and will output a LOW
t
CSD
Tri-State
t
SUCS
OUT
NOTE: Minimum 22 clock cycles required for 16-bit conversion. Shown are 24 clock cycles.
If CS remains LOW at the end of conversion, a new datastream with LSB-first is shifted out again.
Hi-Z
Sample
t
SMPL
MIN
4.5
20
5
CC
OUT
TYP
= 2.7V and above,
16
15
30
20
70
0
5
7
is acceptable, the
(MSB)
B15
Use positive clock edge for data transfer
MAX
100
100
5.0
50
50
25
25
0
B14 B13 B12 B11 B10 B9
Clk Cycles
Clk Cycles
UNITS
kHz
ns
ns
ns
ns
ns
ns
ns
ns
OUT
Conversion
Complete Cycle
10
TABLE II. Ideal Input Voltages and Output Codes.
DATA FORMAT
The output data from the ADS8320 is in Straight Binary
format as shown in Table II. This table represents the ideal
output code for the given input voltage and does not include
the effects of offset, gain error, or noise.
POWER DISSIPATION
The architecture of the converter, the semiconductor fabrica-
tion process, and a careful design allow the ADS8320 to
convert at up to a 100kHz rate while requiring very little
power. Still, for the absolute lowest power dissipation, there
are several things to keep in mind.
The power dissipation of the ADS8320 scales directly with
conversion rate. Therefore, the first step to achieving the
lowest power dissipation is to find the lowest conversion
rate that will satisfy the requirements of the system.
In addition, the ADS8320 is in power down mode under two
conditions: when the conversion is complete and whenever
CS is HIGH (see Figure 3). Ideally, each conversion should
occur as quickly as possible, preferably at a 2.4MHz clock
rate. This way, the converter spends the longest possible
time in the power-down mode. This is very important as the
converter not only uses power on each DCLOCK transition
(as is typical for digital CMOS components) but also uses
some current for the analog circuitry, such as the compara-
tor. The analog section dissipates power continuously, until
the power down mode is entered.
t
DESCRIPTION
Full Scale Range
Least Significant
Bit (LSB)
Full Scale
Midscale
Midscale – 1LSB
Zero
CONV
B8
B7
B6
B5
ANALOG VALUE
V
V
REF
V
B4
REF
REF
V
/2 – 1 LSB
V
REF
/65,536
0V
REF
–1 LSB
B3
/2
B2
B1
1111 1111 1111 1111
1000 0000 0000 0000
0111 1111 1111 1111
0000 0000 0000 0000
(LSB)
B0
BINARY CODE
Power Down
STRAIGHT BINARY
DIGITAL OUTPUT
Hi-Z
HEX CODE
FFFF
7FFF
8000
0000