W90210F Winbond Electronics Corp America, W90210F Datasheet - Page 20

• Manufacturer Part Number: W90210F
• Description: Pa-risc Embedded Controller
• Manufacturer: Winbond Electronics Corp America

Mnemonic
MTDBAO
MFDBAO
MTDBAM
MFDBAM
MTIBAO
MFIBAO
MTIBAM
MFIBAM
DEBUGID
Objects in the memory and I/O system are addressed using 32-bit absolute addresses. An absolute pointer is a 32-bit
unsigned integer whose value is the address of the lowest addressed byte of the operand it designates. The address
mapping is same as that specified by the PA-RISC architecture.
addresses are provided for W90210F CPU core. W90210F CPU core will sample the input pin "PA/486#" at the trailing
edge of RESET to determine the initial instruction address. When PA/486# pin is low, the initial address will be
000FFFF0; when PA/486# is high, it will be EFFFFFF0. This pointer ensures that the program starts execution from
ROM space when used in an X86-compatible board. W90210F CPU core has an internal pull down resistor that will set
W90210F CPU to generate X86-like initial address if the PA/486# is left unconnected.
most privileged. The privilege level is kept in the bits 30 and 31 of the current instruction's address. Base relative branch
instructions (BV, BE and BLE) will demote privilege level to any non zero value, if it changes it. GATEWAY instruction
promotes the privilege level to 0. Other branch instructions have word offset only and will not change privilege level.
5.5 Addressing and access control
The W90210F implements real mode addressing. The total addressable space for the W90210F is 4 GB.
5.5.1 Memory and I/O space
Figure 5.16 shows the memory and I/O address space allocation.
Total memory address space available is (4 GB-256 MB). Total addressable I/O space is 256 MB.
Program address for I/O:
W90210F CPU core output address:
5.5.2 RESET addresses
The initial instruction address after a hardware reset is not defined in the PA-RISC architecture. Two reset
For W90210F, the reset address is always EFFFFFF0.
5.5.3 Access control
Every instruction is fetched and executed at one of four privilege levels (numbered 0,1 2, 3) with 0 being the
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Description
Move to data breakpoint address offset register
Move from data breakpoint address offset register
Move to data breakpoint address mask register
Move from data breakpoint address mask register
Move to instruction breakpoint address offset register
Move from instruction breakpoint address offset register
Move to instruction breakpoint address mask register
Move from instruction breakpoint address mask register
Debug SFU identify
X'EFFFFFFF
X'FFFFFFFF
X'00000000
X'F0000000
Figure 5.16 Memory and I/O addresses
Fxxxxxxx
Table 5.13 Debug SFU instructions
20
0xxxxxxx
Memory Address Space
I/O Address Space
Operation
DBAOR[t] GR[r]
GR[t] DBAOR[r]
DBAMR[t] GR[r]
GR[t] DBAMR[r]
IBAOR[t] GR[r]
GR[t] IBAOR[r]
IBAMR[t] GR[r]
GR[t] IBAMR[r]
GR[t] id number
W90210F
Version 1.4, 10/8/97