PIC16C84 Microchip Technology, PIC16C84 Datasheet - Page 32

• Manufacturer Part Number: PIC16C84
• Description: 8 BIT CMOS EEPROM MICROCONTROLLERS
• Manufacturer: Microchip Technology

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PIC16C84
7.2
EECON1 is the control register with five low order bits
physically implemented. The upper-three bits are non-
existent and read as '0's.
Control bits RD and WR initiate read and write,
respectively. These bits cannot be cleared, only set, in
software. They are cleared in hardware at completion of
the read or write operation. The inability to clear the WR
bit in software prevents the accidental, premature ter-
mination of a write operation.
The WREN bit, when set, will allow a write operation.
On power-up, the WREN bit is clear. The WRERR bit is
set when a write operation is interrupted by a MCLR
reset or a WDT time-out reset during normal operation.
In these situations, following reset, the user can check
the WRERR bit and rewrite the location. The data and
address will be unchanged in the EEDATA and
EEADR registers.
Interrupt flag bit EEIF is set when write is complete. It
must be cleared in software.
EECON2 is not a physical register. Reading EECON2
will read all '0's. The EECON2 register is used
exclusively in the Data EEPROM write sequence.
7.3
To read a data memory location, the user must write
the address to the EEADR register and then set control
bit RD (EECON1<0>). The data is available, in the very
next cycle, in the EEDATA register; therefore it can be
read in the next instruction. EEDATA will hold this value
until another read or until it is written to by the user
(during a write operation).
EXAMPLE 7-1:
DS30445C-page 32
BCF
MOVLW
MOVWF
BSF
BSF
BCF
MOVF
EECON1 and EECON2 Registers
Reading the EEPROM Data Memory
STATUS, RP0
CONFIG_ADDR
EEADR
STATUS, RP0
EECON1, RD
STATUS, RP0
EEDATA, W
DATA EEPROM READ
; Bank 0
;
; Address to read
; Bank 1
; EE Read
; Bank 0
; W = EEDATA
7.4
To write an EEPROM data location, the user must first
write the address to the EEADR register and the data
to the EEDATA register. Then the user must follow a
specific sequence to initiate the write for each byte.
EXAMPLE 7-1:
The write will not initiate if the above sequence is not
exactly followed (write 55h to EECON2, write AAh to
EECON2, then set WR bit) for each byte. We strongly
code segment.
Additionally, the WREN bit in EECON1 must be set to
enable write. This mechanism prevents accidental
writes to data EEPROM due to errant (unexpected)
code execution (i.e., lost programs). The user should
keep the WREN bit clear at all times, except when
updating EEPROM. The WREN bit is not cleared
by hardware
After a write sequence has been initiated, clearing the
WREN bit will not affect this write cycle. The WR bit will
be inhibited from being set unless the WREN bit is set.
At the completion of the write cycle, the WR bit is
cleared in hardware and the EE Write Complete
Interrupt Flag bit (EEIF) is set. The user can either
enable this interrupt or poll this bit. EEIF must be
cleared by software.
recommend that interrupts be disabled during this
Note:
BSF
BCF
BSF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BSF
Writing to the EEPROM Data Memory
The data EEPROM memory E/W cycle
time may occasionally exceed the 10 ms
specification (typical). To ensure that the
write cycle is complete, use the EE
interrupt or poll the WR bit (EECON1<1>).
Both these events signify the completion of
the write cycle.
STATUS, RP0
INTCON, GIE
EECON1, WREN ; Enable Write
55h
EECON2
AAh
EECON2
EECON1,WR
INTCON, GIE
DATA EEPROM WRITE
1997 Microchip Technology Inc.
; Bank 1
; Disable INTs.
;
; Write 55h
;
; Write AAh
; Set WR bit
;
; Enable INTs.
begin write