EPC16xxx Altera, EPC16xxx Datasheet
EPC16xxx
Related parts for EPC16xxx
EPC16xxx Summary of contents
Page 1
... Supports byte-wide configuration mode fast passive parallel (FPP); 8-bit data output per DCLK cycle Supports true n-bit concurrent configuration ( and 8) of Altera FPGAs Pin-selectable 2-ms or 100-ms power-on reset (POR) time Configuration clock supports programmable input source and frequency synthesis Multiple configuration clock sources supported (internal ● ...
Page 2
... The flash memory is used to store configuration data for systems made up of one or more Altera FPGAs. Unused portions of the flash memory can be used to store processor code or data that can be accessed via the external flash interface after FPGA configuration is complete ...
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... This page mode feature combined with the external flash interface allows remote and local updates of system configuration data. The enhanced configuration devices are compatible with the Stratix Remote System Configuration feature. Altera Corporation August 2005 Enhanced Configuration Devices (EPC4, EPC8 & EPC16) Data Sheet JTAG/ISP Interface ...
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... For more information on Stratix Remote System Configuration, refer to the Using Remote System Configuration with Stratix & Stratix GX Devices chapter of the Stratix Device Handbook. Real-time decompression of configuration data Programmable configuration clock (DCLK) Flash ISP Programmable power-on-reset delay (PORSEL) Altera Corporation August 2005 ...
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... MHz). Hence, the flash read bandwidth is limited to about 160 megabits per second (Mbps) (16-bit flash data bus, DQ[], at 10 MHz). However, the configuration speeds supported by Altera FPGAs are much higher and translate to high configuration write bandwidths. For instance, 100-MHz Stratix FPP configuration requires data at the rate of 800 Mbps (8-bit DATA[] bus at 100 MHz) ...
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... Functional Description f For detailed information on using these schemes to configure your Altera FPGA, refer to the appropriate FPGA family chapter in the Configuration Handbook. Configuration Signals Table 2–3 configuration device and Altera FPGAs. Table 2–3. Configuration Signals Enhanced Configuration Device Pin DATA[] DCLK nINIT_CONF ...
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... For specific details on configuration interface connections including pull-up resistor values, supply voltages, and MSEL pin settings, refer to the appropriate FPGA family chapter in the Configuration Handbook. Altera Corporation August 2005 Enhanced Configuration Devices (EPC4, EPC8 & EPC16) Data Sheet Figure 2–2 shows the enhanced configuration device 2– ...
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... GND C-A0 (5) C-A1 (5) C-A15 (5) C-A16 (5) ® II software. To turn off the internal pull-up resistors, check the Disable nCS and Table 2–9. . Additionally, you must make the following pin connections in both CC WE#F RP#F N.C. N.C. N.C. CE# N.C. OE# N.C. V (1) CC VCCW (4) (4) (4) A0-F A1-F A15-F A16-F , TM0 to CC Altera Corporation August 2005 ...
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... PS mode, and connect the least Altera Corporation August 2005 Enhanced Configuration Devices (EPC4, EPC8 & EPC16) Data Sheet While Altera FPGAs can be cascaded in a configuration chain, the enhanced configuration devices cannot be cascaded to configure larger devices/chains. 2–9 ...
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... PS mode using an enhanced configuration device. f For specific details on configuration interface connections including pull-up resistor values, supply voltages, and MSEL pin settings, refer to the appropriate FPGA family chapter in the Configuration Handbook. 2–10 Configuration Handbook, Volume 2 shows the schematic for configuring multiple FPGAs Altera Corporation August 2005 ...
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... PQFP and 88-pin Ultra FineLine BGA packages: C-RP# to F-RP#, C-WE# to F-WE#, TM1 to V GND, and WP (6) Connect the FPGA MSEL[] input pins to select the PS configuration mode. For details, refer to the appropriate FPGA family chapter in the Configuration Handbook. Altera Corporation August 2005 Enhanced Configuration Devices (EPC4, EPC8 & EPC16) Data Sheet V (1) V (1) ...
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... Note to (1) f For configuration schematics and more information on concurrent configuration, refer to Using Altera Enhanced Configuration Devices, chapter 3 in volume 2 of the Configuration Handbook. or the appropriate FPGA family chapter in the Configuration Handbook. External Flash Interface The enhanced configuration devices support external FPGA or processor access to its flash memory ...
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... For further details on the software support for the external flash interface feature, refer to Using Altera Enhanced Configuration Devices, chapter 3 in volume 2 of the Configuration Handbook. For details on flash commands, timing, memory organization, and write protection features, refer to the appropriate flash data sheet (Sharp LHF16306 for EPC16 devices and Micron MT28F400B3 for EPC4 devices) on the Altera web site at www ...
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... Figure 2–4: (1) For external flash interface support in EPC8 enhanced configuration device, contact Altera Applications. (2) Pin A20 in EPC16 devices, pins A20 and A19 in EPC8 devices, and pins A20, A19, and A18 in EPC4 devices should be left floating. These pins should not be connected to any signal, i.e., they are no-connect pins. ...
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... For example, if your system requires three configuration pages and includes two FPGAs, each page will store two SRAM Object Files (.sof) for a total of six SOFs in the configuration device. Altera Corporation August 2005 Enhanced Configuration Devices (EPC4, EPC8 & EPC16) Data Sheet The PGM[2 ...
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... For detailed information on the page mode feature implementation and programming file generation steps using Quartus II software, refer to Using Altera Enhanced Configuration Devices, chapter 3 in volume 2 of the Configuration Handbook. Real-Time Decompression Enhanced configuration devices support on-chip real time decompression of configuration data. FPGA configuration data is compressed by the Quartus II software and stored in the enhanced configuration device ...
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... The compression algorithm used in Altera devices is optimized for FPGA configuration bitstreams. Since FPGAs have several layers of routing structures (for high performance and easy routability), large amounts of resources go unused. These unused routing and logic resources as well as un-initialized memory structures result in a large number of configuration RAM bits in the disabled state ...
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... The maximum DCLK input frequency supported by the FPGA is specified in the appropriate FPGA family chapter in the Configuration Handbook. 2–18 Configuration Handbook, Volume 2 Configuration Device Clock Divider Unit Divide MHz 33 MHz 50 MHz 66 MHz Internal Oscillator Figure 2–5 for a block DCLK Altera Corporation August 2005 ...
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... MHz setting as the clock source, with a divide factor For more information on making the configuration clock source, frequency, and divider settings, refer to Using Altera Enhanced Configuration Devices, chapter 3 in volume 2 of the Configuration Handbook. Flash In-System Programming (ISP) The flash memory inside enhanced configuration devices can be programmed in-system via the JTAG interface and the external flash interface ...
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... For information on protection commands, areas, and lock bits, refer to the appropriate flash memory data sheet (Sharp LHF16506 for EPC16 devices and Micron MT28F400B3 for EPC4 devices) on the Altera web site at www.altera.com. External flash interface programming is only allowed when the configuration controller has relinquished flash access (by tri-stating its internal interface) ...
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... Output DCLK Input nCS nINIT_CONF Open-Drain Output Open-Drain OE Bidirectional Altera Corporation August 2005 Enhanced Configuration Devices (EPC4, EPC8 & EPC16) Data Sheet through 2–9 describe the enhanced configuration device pins. Description This is the configuration data output bus. DATA changes on each falling edge of DCLK ...
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... This flash input is not internally connected to the controller. Hence, an external loop back connection between C-RP# and F-RP# must be made on the board even when you are not using the external flash interface. When using the external flash interface, connect the external device to the RP# pin with the loop back. Altera Corporation August 2005 ...
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... You must connect the two pins at the board level (for example, on the printed circuit board (PCB), connect the C-WE# pin from controller to F-WE# pin from the flash memory). Altera Corporation August 2005 Enhanced Configuration Devices (EPC4, EPC8 & EPC16) Data Sheet ...
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... This pin must be connected to a valid logic level. For normal operation, this test pin must be connected to GND. For normal operating, this test pin must be connected not execute JTAG or ISP instructions until POR is complete ramp time and a CC Altera Corporation August 2005 ...
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... FPGA detects a CRC error or if the FPGA’s nCONFIG input pin is asserted The controller detects a configuration error and asserts OE to initiate re-configuration of the Altera FPGA (for example when CONF_DONE stays low after all configuration data has been transmitted) To ensure the enhanced configuration device enters ...
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... APEX II, APEX 20K, Mercury, ACEX 1K, and FLEX 10K FPGAs into one programming file for the enhanced configuration device. f Refer to Using Altera Enhanced Configuration Devices, chapter 3 in volume 2 of the Configuration Handbook or the Software Settings section in the Configuration Handbook for details on generating programming files. ...
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... Enhanced configuration device instruction register length is 10 and boundary scan length is 174. f For more information on the enhanced configuration device JTAG support, refer to the BSDL files provided at the Altera web site. Enhanced configuration devices can also be programmed by third-party flash programmers or on-board processors using the external flash interface ...
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... IEEE Std. 1149.1 (JTAG) Boundary-Scan You can also program the enhanced configuration devices using the Quartus II software, the Altera Programming Unit (APU), and the appropriate configuration device programming adapter. shows which programming adapter to use with each enhanced configuration device. Table 2–11. Table 10. Programming Adapters ...
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... Update register clock to output JSCO t Update register high-impedance to valid output JSZX t Update register valid output to high impedance JSXZ Altera Corporation August 2005 Enhanced Configuration Devices (EPC4, EPC8 & EPC16) Data Sheet shows the timing parameters and values for the enhanced Parameter Min Max Unit ...
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... For flash memory (external flash interface) timing information, please refer to the corresponding flash data sheet on the Altera web site (Sharp LHF16J06 for EPC16 devices and Micron MT28F400B3 for EPC4 devices). Table 2–13. Enhanced Configuration Device Configuration Parameters (Part ...
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... OUT P Power dissipation D T Storage temperature STG T Ambient temperature AMB T Junction temperature J Altera Corporation August 2005 Enhanced Configuration Devices (EPC4, EPC8 & EPC16) Data Sheet Condition 40% duty cycle 40% duty cycle 40% duty cycle 133 MHz 133 MHz 2 ms 100 ms = 0.5 (DCLK period) - 2.5 ns. OH through 2– ...
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... CC1 CC configuration supply current Note to Table 2–17: (1) For V supply current information, refer to the appropriate flash memory data sheet at www.altera.com. CCW 2–32 Configuration Handbook, Volume 2 Condition Min 3.0 With respect to ground –0.3 0 For commercial use 0 For industrial use –40 ...
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... PCB layer. The EPC8 and EPC4 devices are available in the 100-pin PQFP package. Enhanced configuration devices support vertical migration in the 100-pin PQFP package. Figure 2–8 package. The Gerber file for this layout is on the Altera web site. Altera Corporation August 2005 Enhanced Configuration Devices (EPC4, EPC8 & EPC16) Data Sheet Condition ...
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... Quartus II software. Package Layout Recommendation EPC16 and EPC8 enhanced configuration devices in the 100-pin PQFP packages have different package dimensions than other Altera 100-pin PQFP devices (including EPC4). footprint specifications for enhanced configuration devices that allows for vertical migration between all three devices ...
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... Used 0.5-mm increase for front and back of nominal foot length (2) Used 0.3-mm increase to maximum foot width. f For package outline drawings, refer to the Altera Device Package Information Data Sheet. Altera Corporation August 2005 Enhanced Configuration Devices (EPC4, EPC8 & EPC16) Data Sheet 25.3 mm 0.65-mm pad pitch 19 ...
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... Device Pin-Outs Device Pin-Outs For pin-out information, see the Altera web site at www.altera.com. Ordering Codes Table 2–19 enhanced configuration devices. Table 2–19. Enhanced Configuration Device Ordering Codes 2–36 Configuration Handbook, Volume 2 shows the ordering codes for EPC4, EPC8, and EPC16 Device ...