ISL6334A Intersil Corporation, ISL6334A Datasheet - Page 20

• Manufacturer Part Number: ISL6334A
• Description: 4-Phase PWM Controller
• Manufacturer: Intersil Corporation

When all conditions previously mentioned are satisfied,
ISL6334, ISL6334A begins the soft-start and ramps the
output voltage to 1.1V first. After remaining at 1.1V for some
time, ISL6334, ISL6334A reads the VID code at VID input
pins. If the VID code is valid, ISL6334, ISL6334A will
regulate the output to the final VID setting. If the VID code is
OFF code, ISL6334, ISL6334A will shut down, and cycling
VCC, EN_PWR or EN_VTT is needed to restart.
1. The bias voltage applied at VCC must reach the internal
2. The ISL6334, ISL6334A features an enable input
3. The voltage on EN_VTT must be higher than 0.875V to
ISL6334, ISL6334A INTERNAL CIRCUIT
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FIGURE 8. POWER SEQUENCING USING THRESHOLD-
power-on reset (POR) rising threshold. Once this
threshold is reached, proper operation of all aspects of
the ISL6334, ISL6334A are guaranteed. Hysteresis
between the rising and falling thresholds assure that once
enabled, ISL6334, ISL6334A will not inadvertently turn off
unless the bias voltage drops substantially (see
“Electrical Specifications” table beginning on page 8).
(EN_PWR) for power sequencing between the controller
bias voltage and another voltage rail. The enable
comparator holds the ISL6334, ISL6334A in shutdown
until the voltage at EN_PWR rises above 0.875V. The
enable comparator has about 130mV of hysteresis to
prevent bounce. It is important that the driver reach their
POR level before the ISL6334, ISL6334A becomes
enabled. The schematic in Figure 8 demonstrates
sequencing the ISL6334, ISL6334A with the ISL66xx
family of Intersil MOSFET drivers, which require 12V
bias.
enable the controller. This pin is typically connected to the
output of VTT VR.
FAULT LOGIC
CIRCUIT
SOFT-START
POR
AND
SENSITIVE ENABLE (EN) FUNCTION
COMPARATOR
ENABLE
20
+
-
0.875V
+
0.875V
-
EXTERNAL CIRCUIT
VCC
EN_VTT
EN_PWR
100kΩ
9.1kΩ
+12V
ISL6334, ISL6334A
Soft-Start
ISL6334, ISL6334A based VR has 4 periods during soft-start,
as shown in Figure 9. After VCC, EN_VTT and EN_PWR reach
their POR/enable thresholds, the controller will have a fixed
delay period t
soft-start ramp until the output voltage reaches 1.1V Vboot
voltage. Then, the controller will regulate the VR voltage at 1.1V
for another fixed period t
ISL6334A reads the VID signals. If the VID code is valid,
ISL6334, ISL6334A will initiate the second soft-start ramp until
the voltage reaches the VID voltage minus offset voltage.
The soft-start time is the sum of the 4 periods as shown in
Equation 14.
t
determined by the fixed 85µs plus the time to obtain valid
VID voltage. If the VID is valid before the output reaches the
1.1V, the minimum time to validate the VID input is 500ns.
Therefore, the minimum t
During t
DAC voltage change at 6.25mV per step. The time for each
step is determined by the frequency of the soft-start
oscillator, which is defined by the resistor R
GND. The second soft-start ramp time t
calculated based on Equations 15 and 16:
For example, when VID is set to 1.5V and the R
100kΩ, the first soft-start ramp time t
second soft-start ramp time t
After the DAC voltage reaches the final VID setting,
VR_RDY will be set to high with the fixed delay t
typical value for t
released, the controller disregards the PSI# input and
always operates in normal CCM PWM mode.
t
t
t
D1
SS
D2
D4
is a fixed delay with the typical value as 1.36ms. t
=
=
=
1.1xR
----------------------- - μs
t
(
------------------------------------------------ μs
6.25x25
D1
V
D2
VID
+
and t
6.25x25
FIGURE 9. SOFT-START WAVEFORMS
t
SS
D2
–
D1
1.1
(
+
. After this delay period, the VR will begin first
D4
VOUT, 500mV/DIV
t
)xR
D5
D3
)
, ISL6334, ISL6334A digitally controls the
t
D1
is 85µs. Before the VR_RDY is
+
SS
t
EN_VTT
VR_RDY
D4
(
D3
D3
. At the end of t
)
D4
t
D2
is about 86µs.
500µs/DIV
will be 256µs.
t
D3
D2
t
D4
will be 704µs and the
D2
D3
t
SS
and t
D5
period, ISL6334,
from SS pin to
February 26, 2008
D4
SS
D5
can be
. The
is set at
(EQ. 14)
(EQ. 15)
(EQ. 16)
D3
FN6482.0
is