IDT72V261LA Integrated Device Technology, IDT72V261LA Datasheet - Page 11

• Manufacturer Part Number: IDT72V261LA
• Description: 3.3 Volt Cmos Supersync Fifo
• Manufacturer: Integrated Device Technology

tions may begin starting with the first location in memory. Since IDT
Standard mode is selected, every word read including the first word
following Retransmit setup requires a LOW on REN to enable the rising
edge of RCLK. See Figure 11, Retransmit Timing (IDT Standard Mode),
for the relevant timing diagram.
Retransmit setup by setting OR HIGH. During this period, the internal
read pointer is set to the first location of the RAM array.
time, the contents of the first location appear on the outputs. Since
FWFT mode is selected, the first word appears on the outputs, no LOW
IDT72V261LA/72V271LA
3.3 VOLT CMOS SuperSync FIFO™ 16,384 x 9 and 32,768 x 9
When EF goes HIGH, Retransmit setup is complete and read opera-
If FWFT mode is selected, the FIFO will mark the beginning of the
When OR goes LOW, Retransmit setup is complete; at the same
11
on REN is necessary. Reading all subsequent words requires a LOW
on REN to enable the rising edge of RCLK. See Figure 12, Retransmit
Timing (FWFT Mode), for the relevant timing diagram.
HF and PAF flags begin with the rising edge of RCLK that RT is setup.
PAE is synchronized to RCLK, thus on the second rising edge of RCLK
after RT is setup, the PAE flag will be updated. HF is asynchronous,
thus the rising edge of RCLK that RT is setup will update HF. PAF is
synchronized to WCLK, thus the second rising edge of WCLK that
occurs t
PAF. RT is synchronized to RCLK.
For either IDT Standard mode or FWFT mode, updating of the PAE,
SKEW
after the rising edge of RCLK that RT is setup will update
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES