SI533 Silicon Laboratories, SI533 Datasheet
SI533
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SI533 Summary of contents
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... In addition, DSPLL clock synthesis provides superior supply noise rejection, simplifying the task of generating low jitter clocks in noisy environments typically found in communication systems. The Si533 IC based XO is factory configurable for a wide variety of user specifications including frequency, supply ...
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Electrical Specifications Table 1. Recommended Operating Conditions Parameter 1 Supply Voltage Supply Current www.DataSheet4U.com Output Enable (OE) and Frequency Select (FS) Operating Temperature Range Notes: 1. Selectable parameter specified by part number. See Section 3. "Ordering ...
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... LVPECL/LVDS/CML R, F CMOS with SYM LVPECL: V – 1.3 V (diff) DD LVDS: 1.25 V (diff) CMOS Rev. 1.1 Si533 Min Typ Max — — ±20 — — ±31.5 — — ±61.5 — — 10 — — 10 Min Typ Max V – 1.42 — ...
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Table 4. CLK± Output Phase Jitter Parameter Phase Jitter (RMS)* for F > 500 MHz OUT Phase Jitter (RMS)* for F of 125 to 500 MHz OUT *Note: Differential Modes: LVPECL/LVDS/CML. Refer to AN256 for further information. ...
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... Exposure to maximum rating conditions for extended periods may affect device reliability. 2. The device is compliant with JEDEC J-STD-020C. Refer to Si5xx Packaging FAQ available for download at www.silabs.com/VCXO Table 8. Environmental Compliance The Si533 meets the following qualification test requirements. Mechanical Shock Mechanical Vibration Solderability Gross & Fine Leak ...
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Pin Descriptions OE FS GND www.DataSheet4U.com Pin # Symbol 1 OE* 2 FS* 3 GND 4 CLK+ 5 CLK– *Note: FS and OE include a 17 kΩ pullup resistor to V frequency value ...
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... Part Number Configuration chart below. Silicon Laboratories provides a web browser-based part number configuration utility to simplify this process. Refer to further ordering instructions. The Si533 is supplied in an industry-standard, RoHS compliant, 6-pad package. The Si533 supports output enable (OE) on pin 1. ...
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... Outline Diagram and Suggested Pad Layout Figure 2 illustrates the package details for the Si533. Table 9 lists the values for the dimensions shown in the illustration. www.DataSheet4U.com 8 Figure 2. Si533 Outline Diagram Table 9. Package Diagram Dimensions (mm) Dimension Min Nom A 1.45 1.65 b 1.2 1.4 c 0.60 TYP. D 7.00 BSC. ...
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... Si533 Mark Specification Figure 3 illustrates the mark specification for the Si533. Table 10 lists the line information. www.DataSheet4U.com Line Position 1 1–10 2 1–10 3 Trace Code Position 1 Position 2 Position 3–6 Position 7 Position 8–9 Position SiLabs 123 ...
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... 6-Pin PCB Land Pattern Figure 4 illustrates the 6-pin PCB land pattern for the Si533. Table 11 lists the values for the dimensions shown in the illustration. www.DataSheet4U.com Dimension Notes: 1. Dimensioning and tolerancing per the ANSI Y14.5M-1994 specification. 2. Land pattern design based on IPC-7351 guidelines. ...
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... Revised period jitter specifications. Updated Table 7, “Absolute Maximum Ratings page 5 to reflect the soldering temperature time at 260 ºC is 20–40 sec per JEDEC J-STD-020C. Updated 3. "Ordering Information" on page 7. Changed ordering instructions to revision D. Added 5. "Si533 Mark Specification" on page 9. L IST 1 ,” on Rev. 1.1 ...
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... Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where per- sonal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized ap- plication, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages ...