FAN6520B Fairchild Semiconductor, FAN6520B Datasheet - Page 10

• Manufacturer Part Number: FAN6520B
• Description: Single Synchronous Buck PWM Controller
• Manufacturer: Fairchild Semiconductor

FAN6520B Rev. 1.0.3
P
Where P
rising and falling edges, respectively:
where:
Power MOSFET Selection
For more information on MOSFET selection for synchro-
nous buck regulators, refer to: AN-6005: Synchronous
Buck MOSFET Loss Calculations.
This Fairchild app note is located at:
http://www.fairchildsemi.com/an/AN/AN-6005.pdf
Losses in a MOSFET are the sum of its switching (P
and conduction (P
In typical applications, the FAN6520B converter's output
voltage is low with respect to its input voltage, therefore
the lower MOSFET (Q2) is conducting the full load cur-
rent for most of the cycle. Therefore choose a MOSFET
for Q2 which has low R
losses.
In contrast, the high-side MOSFET (Q1) has a much
shorter duty cycle, and its conduction loss will therefore
have less of an impact. Q1, however, sees most of the
switching losses, so Q1’s primary selection criteria
should be gate charge.
High-Side Losses
Figure 9 shows a MOSFET’s switching interval, with the
upper graph being the voltage and current on the Drain
to Source and the lower graph detailing V
a constant current charging the gate. The x-axis, there-
fore, is also representative of gate charge (Q
C
receives the current from the gate driver during t3 (as
V
lower graph are either specified or can be derived from
the MOSFET’s datasheet.
Assuming switching losses are about the same for both
the rising edge and falling edge, Q1’s switching losses,
occur during the shaded time when the MOSFET has
voltage across it and current through it.
LDRV
DS
GD
P
P
P
P
LDRV
Q2
is falling). The gate charge (Q
L F
L R
+ C
is dissipation of the lower FET driver.
= Q
H(R)
GS
= P
=
=
G2
, and it controls t1, t2, and t4 timing. C
P
P
L(R)
Q2
and P
Q2
V
GS(Q2)
COND
------------------------------------------- -
R
------------------------------------------ -
R
P
H(F)
HDN
LUP
L(F)
) losses.
R
R
are internal dissipations for the
+
+
DS(ON)
LDN
LUP
F
R
R
SW
E
E
+
+
R
R
to minimize conduction
G
G
G
) parameters on the
GS
vs. time with
G
) . C
ISS
(11)
(12)
(10)
(13)
SW
GD
=
)
10
These losses are given by:
where:
P
and P
given MOSFET. R
perature (T
and is t2+t3 (Figure 9).
The driver’s impedance and C
period is controlled by the driver’s impedance and Q
Since most of t
constant current assumption for the driver to simplify the
calculation of t
UPPER
V
V
V
P
P
P
DS
V
I
COND
TH
GS
UPPER
SW
D
COND
SP
5V
is the upper MOSFET’s total losses, and P
R
Figure 9. Switching Losses and Q
Figure 10. Drive Equivalent Circuit
=
D
J
are the switching and conduction losses for a
). t
= P
=
V
---------------------
S
S
t1
DS
S
:
C
SW
V
--------------
is the switching period (rise or fall time)
2
Q
V
occurs when V
DS(ON)
ISS
OUT
GS
IN
+ P
I
L
t2
COND
SW
HDRV
2 t
is at the maximum junction tem-
I
Q
OUT
G(SW)
s
2
ISS
C
F
Q
GD
SW
GS
GD
t3
G
R
determine t2 while t3’s
DS ON
= V
R
GATE
SP
C
C
t4
we can use a
GS
www.fairchildsemi.com
C
GD
ISS
G
t5
4.5V
VIN
(14)
(15)
GD
SW
.