74ABT374 Fairchild Semiconductor, 74ABT374 Datasheet

no-image

74ABT374

Manufacturer Part Number
74ABT374
Description
Octal D-Type Flip-Flop with 3-STATE Outputs
Manufacturer
Fairchild Semiconductor
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
74ABT374A
Manufacturer:
PHILIPS
Quantity:
1 188
Part Number:
74ABT374AD
Manufacturer:
PHILIPS
Quantity:
101
Part Number:
74ABT374AD
Manufacturer:
NXP/恩智浦
Quantity:
20 000
Part Number:
74ABT374AN
Manufacturer:
PHILIPS
Quantity:
275
Part Number:
74ABT374APW
Manufacturer:
PHILIPS/飞利浦
Quantity:
20 000
Part Number:
74ABT374CMSA
Manufacturer:
FAIRCHILD/仙童
Quantity:
20 000
Part Number:
74ABT374CSCX
Manufacturer:
FAIRCHILD/仙童
Quantity:
20 000
Part Number:
74ABT374CST
Manufacturer:
TI
Quantity:
96
Part Number:
74ABT374D
Manufacturer:
PHILIPS
Quantity:
3 910
© 1999 Fairchild Semiconductor Corporation
74ABT374CSC
74ABT374CSJ
74ABT374CMSA
74ABT374CMTC
74ABT374CPC
74ABT374
Octal D-Type Flip-Flop with 3-STATE Outputs
General Description
The ABT374 is an octal D-type flip-flop featuring separate
D-type inputs for each flip-flop and 3-STATE outputs for
bus-oriented applications. A buffered Clock (CP) and Out-
put Enable (OE) are common to all flip-flops.
Ordering Code:
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagram
Order Number
Package Number
MSA20
MTC20
M20B
M20D
N20A
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
DS011510
Features
Pin Descriptions
Pin Names
Edge-triggered D-type inputs
Buffered positive edge-triggered clock
3-STATE outputs for bus-oriented applications
Output sink capability of 64 mA, source capability of
32 mA
Guaranteed output skew
Guaranteed multiple output switching specifications
Output switching specified for both 50 pF and 250 pF
loads
Guaranteed simultaneous switching, noise level and
dynamic threshold performance
Guaranteed latchup protection
High impedance glitch free bus loading during entire
power up and power down cycle
Non-destructive hot insertion capability
D
CP
OE
O
0
0
–D
–O
Package Description
7
7
Data Inputs
Clock Pulse Input (Active Rising Edge)
3-STATE Output Enable Input (Active LOW)
3-STATE Outputs
Description
November 1992
Revised November 1999
www.fairchildsemi.com

Related parts for 74ABT374

74ABT374 Summary of contents

Page 1

... M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74ABT374CMSA MSA20 20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide 74ABT374CMTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74ABT374CPC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Device also available in Tape and Reel. Specify by appending suffix letter “ ...

Page 2

Functional Description The ABT374 consists of eight edge-triggered flip-flops with individual D-type inputs and 3-STATE true outputs. The buffered clock and buffered Output Enable are common to all flip-flops. The eight flip-flops will store the state of their individual D ...

Page 3

Absolute Maximum Ratings Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias V Pin Potential to CC Ground Pin Input Voltage (Note 2) Input Current (Note 2) Voltage Applied to Any Output in the Disabled or Power-Off State in ...

Page 4

DC Electrical Characteristics (SOIC package) Symbol Parameter V Quiet Output Maximum Dynamic V OLP OL V Quiet Output Minimum Dynamic V OLV OL V Minimum HIGH Level Dynamic Output Voltage OHV V Minimum HIGH Level Dynamic Input Voltage IHD V ...

Page 5

Extended AC Electrical Characteristics (SOIC Package Symbol Parameter 8 Outputs Switching Min t Propagation Delay 1.5 PLH 1.5 PHL n t Output Enable Time 1.5 PZH t 1.5 PZL t Output Disable ...

Page 6

AC Loading *Includes jig and probe capacitance FIGURE 1. Standard AC Test Load Amplitude 3.0V FIGURE 3. Test Input Signal Requirements AC Waveforms FIGURE 4. Propagation Delay Waveforms for Inverting and Non-Inverting Functions FIGURE 5. Propagation Delay, Pulse Width Waveforms ...

Page 7

Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body Package Number M20B 7 www.fairchildsemi.com ...

Page 8

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide www.fairchildsemi.com Package Number M20D 8 ...

Page 9

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide Package Number MSA20 9 www.fairchildsemi.com ...

Page 10

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide www.fairchildsemi.com Package Number MTC20 10 ...

Page 11

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MO-001, 0.300” Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right ...

Related keywords