LM4548A National Semiconductor, LM4548A Datasheet
LM4548A
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LM4548A Summary of contents
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... AC ’97 Rev 2 Multi-Channel Audio Codec with Sample Rate Conversion and National 3D Sound General Description The LM4548A is an audio codec for PC systems which is fully PC98 compliant and performs the analog intensive functions of the AC ’97 Rev 2 architecture. Using 18-bit Sigma-Delta ADCs and DACs, the LM4548A provides Dynamic Range ...
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... CD Left to Right 22 -34 215˚C 220˚C 74˚C/W −40˚C ≤ T ≤ 85˚C (Note 4) MAX A 4.2V ≤ AV ≤ 5.5V DD 3.0V ≤ DV ≤ Units LM4548A (Limits) Typical Limit (Note 6) (Note 7) 4.2 V (min) 5.5 V (max) 3.0 V (min) 5.5 V (max 500 µA 30 µ ...
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... Hold time of SDATA_OUT from falling edge of BIT_CLK SYNC to rising edge of BIT_CLK Hold time of SYNC from rising edge of BIT_CLK 25˚C. The reference for Vrms unless A LM4548A Typical Limit (Note 6) (Note kΩ ...
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... Delay from end of Slot 2 to BIT_CLK, SDATA_IN low Time from minimum valid supply levels to end of Reset For ATE Test Mode For ATE Test Mode – T )/θ or the number given in Absolute Maximum Ratings, whichever is lower. For the LM4548A, T JMAX 5V 5V ...
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Timing Diagrams www.national.com www.DataSheet.in Clocks 20030010 Digital Rise and Fall 20030012 Power On Reset Cold Reset Warm Reset Data Delay, Setup and Hold Legend 20030030 20030013 20030014 6 20030011 20030029 ...
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... Typical Application FIGURE 1. LM4548A Typical Application Circuit, Single Codec, 1 Vrms inputs APPLICATION HINTS • The LM4548A must be initialized by using RESET# to perform a Power On Reset as shown in the Power On Reset Timing Diagram • V must be pulled high to AV REF • Don’t leave unused inputs floating. Tie all unused inputs together and connect to Analog Ground through a capacitor (e.g. 0.1 µ ...
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... I PHONE 13 I www.DataSheet.in Top View Order Number LM4548AVH See NS Package Number VBH48A ANALOG I/O Functional Description Mono Input This line level (1 Vrms nominal) mono input is mixed equally into both channels of the Stereo Mix signal at MIX2 under the control of the PC_Beep Volume control register, 0Ah. The PC_BEEP level can be muted or adjusted from - steps ...
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Pin Descriptions Name Pin AUX_L AUX_R VIDEO_L VIDEO_R CD_L CD_GND CD_R www.national.com www.DataSheet.in (Continued) ANALOG I/O (Continued Functional Description Left Stereo Channel Input This line level input (1 Vrms nominal) is selectable at the left channel of ...
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Pin Descriptions Name Pin MIC1 21 I MIC2 22 I LINE_IN_L 23 I LINE_IN_R 24 I LINE_OUT_L 35 O LINE_OUT_R 36 O MONO_OUT 37 O www.DataSheet.in (Continued) ANALOG I/O (Continued) Functional Description Mono microphone input Either MIC1 ...
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... AC Link clock generated by a Primary Codec. Output from codec This is the output for AC Link Input Frames from the LM4548A codec ’97 Digital O Audio Controller. These frames can contain both codec status data and PCM audio data from the ADCs ...
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... Cold Reset This active low signal causes a hardware reset which returns the control registers and all internal circuits to their default conditions. RESET# must be used to initialize the LM4548A after Power On when the supplies have stabilized. Cold Reset also clears the codec from both ATE and Vendor test modes ...
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Typical Performance Characteristics www.national.com www.DataSheet.in ADC Noise Floor 20030015 Line Out Noise Floor (Analog Loopthrough) 20030018 ADC Frequency Response 20030019 DAC Noise Floor Line Level Out Noise Floor (Analog Loopthrough) DAC Frequency Response 14 20030016 20030031 20030020 ...
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Volume Output www.DataSheet.in Volume Input Sources ADC 15 www.national.com ...
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... Functional Description GENERAL The LM4548A codec can mix, process and convert among analog (stereo and mono) and digital (AC Link format) inputs and outputs. There are four stereo and four mono analog inputs and two stereo and one mono analog outputs. A single codec supports data streaming on two input and two output channels of the AC Link digital interface simultaneously ...
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... Data Slots. With the codec in Primary mode, a controller will indicate valid data in a slot by setting the associated tag bit equal to 1. Since two channel codec the LM4548A can only receive data from four slots in a given frame and so only 17 ...
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... AC ’97 controller. 18:12 SDATA_OUT: Slot 2 – Control Data Slot 2 is used to transmit 16-bit control data to the LM4548A when the access operation is ’write’. The least significant four bits should be stuffed with zeros by the AC ’97 controller. If the access operation is a register read, the entire slot, bits 19 through 0 should be stuffed with zeros ...
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... Frames are constructed from thirteen time slots: one Tag Slot followed by twelve Data Slots. The Tag Slot, Slot 0, contains 16 bits of which 5 are used by the LM4548A. One is used to indicate that the AC Link interface is fully operational and the other 4 to indicate the validity of the data in the four of the twelve following Data Slots that are used by the LM4548A ...
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... Hz, then only those one-in-six audio samples that follow a Slot Request will be used by the DAC. The rest will be discarded. Bits 9 – 2 are request bits for slots not used by the LM4548A and are stuffed with zeros. Bits 1 and 0 are reserved and are also stuffed with zeros. ...
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... PCM sample from right 19:2 Right Channel ADC data 1:0 Reserved Stuffed with "0"s by LM4548A SDATA_IN: Slots – Reserved Slots 5 – the AC Link Input Frame are not used for data by the LM4548A and are always stuffed with zeros. 21 www.national.com ...
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... RESET REGISTER (00h) Writing any value to this register causes a Register Reset which changes all registers back to their default values read is performed on this register, the LM4548A will return a value of 0D40h. This value can be interpreted in accordance with the AC ’97 specification to indicate that National 3D Sound is implemented and 18-bit data is supported for both the ADCs and DACs ...
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... Loopback EXTENDED AUDIO ID REGISTER (28h) This read-only register identifies which AC ’97 Extended Audio features are supported. The LM4548A features VRA (Variable Rate Audio) and ID1, ID0 (Multiple Codec support). VRA is indicated by a "1" in bit 0. The two MSBs, ID1 and ID0, show the current Codec Identity as defined by the ...
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... LM4548A Register Map are reserved. Reserved regis- ters will return 0000h if read. Low Power Modes The LM4548A provides 6 bits to control the powerdown state of internal analog and digital subsections and clocks. These 6 bits (PR0 – PR5) are located in the 8 MSBs of the Pow- erdown Control/Status register, 26h ...
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Low Power Modes Improving System Performance The audio codec is capable of dynamic range performance in excess of 90 db., but the user must pay careful attention to several factors to achieve this. A primary consideration is keeping analog and ...
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Multiple Codecs When reading from a Secondary Codec, the controller must send the correct Codec ID bits (i.e. the target Codec Identity in slot 0, bits 1 and 0) along with the read-request bit (slot 1, bit 19) and target ...
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Multiple Codecs (Continued) Test Modes AC ’97 Rev 2 defines two test modes: ATE test mode and Vendor test mode. Cold Reset is the only way to exit either of them. The ATE test mode is activated if SDATA_OUT is ...
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... National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. www.DataSheet.in inches (millimeters) unless otherwise noted 48-Lead , LQFP 1.4mm, JEDEC (M) Order Number LM4548AVH NS Package Number VBH48A 2. A critical component is any component of a life support device or system whose failure to perform ...