MC705P6A Motorola, MC705P6A Datasheet - Page 35

• Manufacturer Part Number: MC705P6A
• Description: Microcontrollers
• Manufacturer: Motorola

5.2 Interrupt Types
The interrupts fall into three categories: reset, software, and hardware.
5.2.1 Reset Interrupt Sequence
The reset function is not in the strictest sense an interrupt; however, it is acted upon in a similar manner
as shown in
the program to vector to its starting address which is specified by the contents of memory locations $1FFE
and $1FFF. The I bit in the condition code register is also set. The MCU is configured to a known state
during this type of reset as previously described in
5.2.2 Software Interrupt (SWI)
The SWI is an executable instruction. It is also a non-maskable interrupt since it is executed regardless
of the state of the I bit in the CCR. As with any instruction, interrupts pending during the previous
instruction will be serviced before the SWI opcode is fetched. The interrupt service routine address for the
SWI instruction is specified by the contents of memory locations $1FFC and $1FFD.
5.2.3 Hardware Interrupts
All hardware interrupts are maskable by the I bit in the CCR. If the I bit is set, all hardware interrupts
(internal and external) are disabled. Clearing the I bit enables the hardware interrupts. Four hardware
interrupts are explained in the following subsections.
5.2.3.1 External Interrupt (IRQ)
The IRQ/V
falling edge of IRQ/V
IRQ/V
in the mask option register is clear (edge-sensitive only), the output of the internal edge detector flip-flop
is sampled and the input level on the IRQ/V
specified by the contents of memory locations $1FFA and $1FFB. If the port A interrupts are enabled by
the MOR, they generate external interrupts identically to the IRQ/V
5.2.3.2 Input Capture Interrupt
The input capture interrupt is generated by the 16-bit timer as described in
Timer. The input capture interrupt flag is located in register TSR and its corresponding enable bit can be
found in register TCR. The I bit in the CCR must be clear for the input capture interrupt to be enabled. The
interrupt service routine address is specified by the contents of memory locations $1FF8 and $1FF9.
Freescale Semiconductor
PP
pin is low, a request is synchronized to the CPU to generate the IRQ interrupt. If the LEVEL bit
PP
Figure
pin drives an asynchronous interrupt to the CPU. An edge detector flip-flop is latched on the
The internal interrupt latch is cleared nine internal clock cycles after the
interrupt is recognized (immediately after location $1FFA is read).
Therefore, another external interrupt pulse could be latched during the IRQ
service routine.
Another interrupt will be serviced if the IRQ pin is still in a low state when
the RTI in the service routine is executed.
5-1. A low-level input on the RESET pin or internally generated RST signal causes
PP
. If either the output from the internal edge detector flip-flop or the level on the
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
PP
pin is ignored. The interrupt service routine address is
NOTE
Chapter 4
Resets.
PP
pin.
Chapter 8 Capture/Compare
Interrupt Types
35