74HC40105N,652 NXP Semiconductors, 74HC40105N,652 Datasheet - Page 18

• Manufacturer Part Number: 74HC40105N,652
• Description: IC FIFO REGISTER 4X16 16DIP
• Manufacturer: NXP Semiconductors
• Series: 74HCr

Specifications of 74HC40105N,652

• Function: Asynchronous
• Memory Size: 64 (4 x 16)
• Data Rate: 25MHz
• Voltage - Supply: 2 V ~ 6 V
• Mounting Type: Through Hole
• Package / Case: 16-DIP (0.300", 7.62mm)
• Logic Family: HC
• Logical Function: FIFO Register
• Number Of Elements: 1
• Number Of Bits: 4
• Number Of Inputs: 4
• Number Of Outputs: 4
• High Level Output Current: -7.8mA
• Low Level Output Current: 7.8mA
• Propagation Delay Time: 750ns
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 6V
• Operating Supply Voltage (min): 2V
• Output Type: 3-State
• Polarity: Non-Inverting
• Technology: CMOS
• Frequency (max): 36(Typ)MHz
• Mounting: Through Hole
• Pin Count: 16
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Quiescent Current: 8uA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Access Time: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 74HC40105N; 74HC40105N; 933669660652

Philips Semiconductors
1998 Jan 23
4-bit x 16-word FIFO register
(1) HC : V
Fig.20 FIFO to FIFO communication; input timing under
(1) HC : V
Fig.21 FIFO to FIFO communication; output timing under
HCT : V
HCT : V
empty condition.
full condition.
M
M
M
M
= 50%; V
= 50%; V
= 1.3 V; V
= 1.3 V; V
I
I
I
I
= GND to V
= GND to V
= GND to 3 V.
= GND to 3 V.
CC
CC
.
.
18
Notes to Fig.20
1. FIFO
2. Load one word into FIFO
3. Data out
4. DOR
5. DIR
6. DIR
7. DOR
Notes to Fig.21
1. FIFO
2. Unload one word into FIFO
3. DIR
4. DOR
5. DOR
6. DIR
HIGH in anticipation of data.
results in DIR pulse.
arrives at FIFO
delay of the DOR flag, meeting data input
set-up requirements of FIFO
delay after SI
FIFO
pulse, data is shifted into FIFO
stage of FIFO
complete.
input stage of FIFO
data, SO is held HIGH in anticipation of
additional data.
SI
propagation delay later at the FIFO
stage.
HIGH in anticipation of shifting in new data as
empty location bubbles-up.
applied, results in DOR pulse.
after SO
a result of the DIR pulse, data is shifted out of
FIFO
output stage of FIFO
FIFO
data is again available at FIFO
SI
empty location.
SO
input stage of FIFO
B
B
A
B
B
LOW) valid data is present one
B
is held HIGH, awaiting bubble-up of
A
A
B
A
A
LOW) an empty location is present at
A
A
A
A
R
and SO
and SO
and SO
.
goes HIGH; (bubble-up delay after
and SI
goes HIGH; (ripple through delay after
and SI
and SI
and FIFO
and FIFO
is complete.
as a result of the data output ready
B
A
LOW) data is loaded into FIFO
/data in
A
B
A
A
A
B
B
B
A
pulse HIGH; (bubble-up delay
pulse HIGH; (ripple through
LOW) data is unloaded from
go LOW; flag indicates input
go HIGH automatically; the
go LOW; flag indicates the
go HIGH; flag indicates valid
is busy, shift-out of FIFO
B
output stage after a specified
B
74HC/HCT40105
initially empty, SO
initially empty, SI
B
B
A
transition; valid data
.
A
is again able to receive
is busy, shift-in to
Product specification
A
; SI pulse applied,
B
; SO pulse
B
.
A
B
.
output stage,
B
B
A
output
held
held
A
B
is
as