HT46801N-1 Holtek Semiconductor, HT46801N-1 Datasheet - Page 37

• Manufacturer Part Number: HT46801N-1
• Description: (HT4xR01x-1) Small Package 8-Bit OTP MCU
• Manufacturer: Holtek Semiconductor

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register and continue counting. The interrupt can be dis-
abled by ensuring that the Timer/Event Counter Inter-
rupt Enable bit in the corresponding Interrupt Control
Register, is reset to zero.
As the external timer pin is shared with an I/O pin, to en-
sure that the pin is configured to operate as an event
counter input pin, two things have to happen. The first is
to ensure that the Operating Mode Select bits in the
Timer Control Register place the Timer/Event Counter in
the Event Counting Mode, the second is to ensure that
the port control register configures the pin as an input. It
should be noted that in the event counting mode, even if
t h e microcontroller i s i n th e Sl ee p Mod e, the
Timer/Event Counter will continue to record externally
changing logic events on the timer input TCn pin. As a
result when the timer overflows it will generate a timer
interrupt and corresponding wake-up source.
Pulse Width Capture Mode
In this mode, the Timer/Event Counter can be utilised to
measure the width of external pulses applied to the ex-
ternal timer pin. To operate in this mode, the Operating
Mode Select bit pair, TnM1/TnM0, in the Timer Control
Register must be set to the correct value as shown.
In this mode the internal clock, f
oscillator, is used as the internal clock determined by
which Timer/Event Counter is selected to be used. The
internal clock source for the Timer/Event Counter 0 is
further divided by a prescaler, the value of which is de-
termined by the Prescaler Rate Select bits named
T0PSC2~T0PSC0, which are bits 2~0 in the Timer Con-
trol Register. After other bits in the Timer Control Regis-
ter have been setup, the enable bit TnON, which is bit 4
of the Timer Control Register, can be set high to enable
the Timer/Event Counter, however it will not actually
start counting until an active edge is received on the ex-
ternal timer pin.
If the Active Edge Select bit TnEG, which is bit 3 of the
Timer Control Register, is low, once a high to low transi-
tion has been received on the external timer pin, the
Timer/Event Counter will start counting until the external
Rev.1.00
Control Register Operating Mode
Select Bits for the Pulse Width
Capture Mode
Pulse Width Capture Mode Timing Chart (TnEG=0)
SYS
, f
SYS
/4 or the LXT
Bit7 Bit6
1
1
37
timer pin returns to its original high level. At this point the
enable bit will be automatically reset to zero and the
Timer/Event Counter will stop counting. If the Active
Edge Select bit is high, the Timer/Event Counter will be-
gin counting once a low to high transition has been re-
ceived on the external timer pin and stop counting when
the external timer pin returns to its original low level. As
before, the enable bit will be automatically reset to zero
and the Timer/Event Counter will stop counting. It is im-
portant to note that in the pulse width capture Mode, the
enable bit is automatically reset to zero when the exter-
nal control signal on the external timer pin returns to its
original level, whereas in the other two modes the en-
able bit can only be reset to zero under program control.
The residual value in the Timer/Event Counter, which
can now be read by the program, therefore represents
the length of the pulse received on the TCn pin. As the
enable bit has now been reset, any further transitions on
the external timer pin will be ignored. The timer cannot
begin further pulse width capture until the enable bit is
set high again by the program. In this way, single shot
pulse measurements can be easily made.
It should be noted that in this mode the Timer/Event
Counter is controlled by logical transitions on the external
timer pin and not by the logic level. When the Timer/Event
Counter is full and overflows, an interrupt signal is gener-
ated and the Timer/Event Counter will reload the value al-
ready loaded into the preload register and continue
counting. The interrupt can be disabled by ensuring that
the Timer/Event Counter Interrupt Enable bit in the corre-
sponding Interrupt Control Register, is reset to zero.
As the TCn pin is shared with an I/O pin, to ensure that
the pin is configured to operate as a pulse width capture
pin, two things have to happen. The first is to ensure that
the Operating Mode Select bits in the Timer Control
Register place the Timer/Event Counter in the pulse
width capture Mode, the second is to ensure that the
port control register configures the pin as an input.
Prescaler
Bits T0PSC0~T0PSC2 of the TMR0C register can be
used to define a division ratio for the internal clock
source of the Timer/Event Counter 0 enabling longer
time out periods to be setup.
HT46R01B-1/HT46R01N-1
HT48R01B-1/HT48R01N-1
June 9, 2011
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