25C640 Microchip Technology, Inc., 25C640 Datasheet - Page 7

• Manufacturer Part Number: 25C640
• Description: The 25AA640 is a 64K-bit Serial Electrically Erasable Prom With Memory Accessed Via a Simple Serial Peripheral Interface (SPI™) Compatible Serial Bus
• Manufacturer: Microchip Technology, Inc.

2.0
The descriptions of the pins are listed in Table 2-1.
TABLE 2-1:
2.1
A low level on this pin selects the device. A high level
deselects the device and forces it into standby mode.
However, a programming cycle which is already initi-
ated or in progress will be completed, regardless of the
CS input signal. If CS is brought high during a program
cycle, the device will go into standby mode when the
programming cycle is complete. When the device is
deselected, SO goes to the high impedance state,
allowing multiple parts to share the same SPI bus. A
low to high transition on CS after a valid write sequence
initiates an internal write cycle. After power-up, a high
to low transition on CS is required prior to any
sequence being initiated.
2.2
The SO pin is used to transfer data out of the 25XX640.
During a read cycle, data is shifted out on this pin after
the falling edge of the serial clock.
2.3
This pin is used in conjunction with the WPEN bit in the
status register to prohibit writes to the non-volatile bits
in the status register. When WP is low and WPEN is
high, writing to the non-volatile bits in the status register
is disabled. All other operations function normally.
When WP is high, all functions, including writes to the
non-volatile bits in the status register operate normally.
If the WPEN bit is set, WP low during a status register
write sequence will disable writing to the status register.
If an internal write cycle has already begun, WP going
low will have no effect on the write.
The WP pin function is blocked when the WPEN bit in
the status register is low. This allows the user to install
the 25AA640/25LC640 in a system with WP pin
grounded and still be able to write to the status register.
The WP pin functions will be enabled when the WPEN
bit is set high.
HOLD
Name
SCK
2001 Microchip Technology Inc.
V
V
WP
SO
CS
SI
CC
SS
PIN DESCRIPTIONS
Chip Select (CS)
Serial Output (SO)
Write Protect (WP)
PDIP
1
2
3
4
5
6
7
8
PIN FUNCTION TABLE
SOIC
1
2
3
4
5
6
7
8
TSSOP
3
4
5
6
7
8
1
2
Chip Select Input
Serial Data Output
Write Protect Pin
Ground
Serial Data Input
Serial Clock Input
Hold Input
Supply Voltage
Description
2.4
The SI pin is used to transfer data into the device. It
receives instructions, addresses, and data. Data is
latched on the rising edge of the serial clock.
2.5
The SCK is used to synchronize the communication
between a master and the 25XX640. Instructions,
addresses, or data present on the SI pin are latched on
the rising edge of the clock input, while data on the SO
pin is updated after the falling edge of the clock input.
2.6
The HOLD pin is used to suspend transmission to the
25XX640 while in the middle of a serial sequence with-
out having to re-transmit the entire sequence over
again. It must be held high any time this function is not
being used. Once the device is selected and a serial
sequence is underway, the HOLD pin may be pulled
low to pause further serial communication without
resetting the serial sequence. The HOLD pin must be
brought low while SCK is low, otherwise the HOLD
function will not be invoked until the next SCK high to
low transition. The 25XX640 must remain selected dur-
ing this sequence. The SI, SCK, and SO pins are in a
high impedance state during the time the device is
paused and transitions on these pins will be ignored. To
resume serial communication, HOLD must be brought
high while the SCK pin is low, otherwise serial commu-
nication will not resume. Lowering the HOLD line at any
time will tri-state the SO line.
25AA640/25LC640
Serial Input (SI)
Serial Clock (SCK)
Hold (HOLD)
DS21223E-page 7