IDT72V261LA10TF IDT, Integrated Device Technology Inc, IDT72V261LA10TF Datasheet - Page 8

• Manufacturer Part Number: IDT72V261LA10TF
• Description: IC FIFO SS 8192X18 10NS 64QFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Vr

Specifications of IDT72V261LA10TF

• Function: Synchronous
• Memory Size: 144K (8K x 18)
• Data Rate: 100MHz
• Access Time: 10ns
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 64-STQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72V261LA10TF

PROGRAMMING FLAG OFFSETS
IDT72V261LA/72V271LA has internal registers for these offsets. De-
fault settings are stated in the footnotes of Table 1 and Table 2. Offset
values can be programmed into the FIFO in one of two ways; serial or
parallel loading method. The selection of the loading method is done
using the LD (Load) pin. During Master Reset, the state of the LD input
determines whether serial or parallel flag offset programming is en-
abled. A HIGH on LD during Master Reset selects serial loading of
offset values and in addition, sets a default PAE offset value of 3FFH (a
threshold 1,023 words from the empty boundary), and a default PAF
offset value of 3FFH (a threshold 1,023 words from the full boundary).
A LOW on LD during Master Reset selects parallel loading of offset
TABLE 1 — STATUS FLAGS FOR IDT STANDARD MODE
NOTES:
1. n = Empty Offset, Default Values: n = 127 when parallel offset loading is selected or n = 1,023 when serial offset loading is selected.
2. m = Full Offset, Default Values: m = 127 when parallel offset loading is selected or m = 1,023 when serial offset loading is selected.
TABLE 2 — STATUS FLAGS FOR FWFT MODE
NOTES:
1. n = Empty Offset, Default Values: n = 127 when parallel offset loading is selected or n = 1,023 when serial offset loading is selected.
2. m = Full Offset, Default Values: m = 127 when parallel offset loading is selected or m = 1,023 when serial offset loading is selected.
IDT72V261LA/72V271LA
3.3 VOLT CMOS SuperSync FIFO™ 16,384 x 9 and 32,768 x 9
Full and Empty Flag offset values are user programmable. The
Words in
FIFO
Words in
FIFO
Number of
Number of
(1)
(16,384-m)
8,194 to (16,385-(m+1))
8,193 to (16,384-(m+1))
(16,385-m) to 16,384
(n + 1) to 8,192
(n + 2) to 8,193
IDT72V261LA
IDT72V271LA
1 to n+1
1 to n
16,384
16,385
(2)
0
0
to 16,383
(1)
(1)
(2)
8
values, and in addition, sets a default PAE offset value of 07FH (a
threshold 127 words from the empty boundary), and a default PAF
offset value of 07FH (a threshold 127 words from the full boundary).
See Figure 3, Offset Register Location and Default Values.
the current offset values. It is only possible to read offset values via parallel
read.
rizes the control pins and sequence for both serial and parallel program-
ming modes. For a more detailed description, see discussion that follows.
after Master Reset, regardless of whether serial or parallel programming
has been selected.
In addition to loading offset values into the FIFO, it also possible to read
Figure 4, Programmable Flag Offset Programming Sequence, summa-
The offset registers may be programmed (and reprogrammed) any time
16,386 to (32,769-(m+1))
(32,768-m)
(32,769-m)
16,385 to (32,768-(m+1))
(n + 1) to 16,384
(n + 2) to 16,385
IDT72V261LA
IDT72V271LA
1 to n+1
1 to n
32,768
32,769
0
0
(2)
(2)
(1)
to 32,767
to 32,768
(1)
(2)
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
FF PAF
FF PAF
H
H
H
H
H
H
L
L
L
L
L
L
JANUARY 30, 2009
H
H
H
H
H
H
H
H
L
L
L
L
HF
HF
H
H
H
H
H
H
L
L
L
L
L
L
PAE EF
PAE EF
H
H
H
H
H
H
H
H
L
L
L
L
H
H
H
H
H
H
L
L
L
L
L
L