AD8364ACPZ-R2 Analog Devices, AD8364ACPZ-R2 Datasheet - Page 18

• Manufacturer Part Number: AD8364ACPZ-R2
• Description: LF to 2.7GHz, Dual 60dB TruPwr Detector
• Manufacturer: Analog Devices

AD8364
GENERAL DESCRIPTION AND THEORY
The AD8364 is a dual-channel, 2.7 GHz, true rms responding
detector with 60 dB measurement range. It incorporates two
AD8362 channels with shared reference circuitry (See the
AD8362 datasheet for more information). Multiple enhancements
have been made to the AD8362 cores to improve measurement
accuracy. Log-conformance peak-to-peak ripple has been reduced
to <±0.2 dB over the entire dynamic range. Temperature stability
of the rms output measurements provides <±0.5 dB error over
the specified temperature range of −40°C to 85°C through
proprietary techniques. The use of well-matched channels offers
extremely temperature-stable difference outputs, OUTP and
OUTN. Given well-matched channels through IC integration,
the rms measurement outputs, OUTA and OUTB, drift in the
same manner. With OUTP shorted to FBKA, the function at
OUTP is
When OUTN is shorted to FBKB, the function at OUTN is
OUTP and OUTN are insensitive to the common drift due to
the difference cancellation of OUTA and OUTB.
The AD8364 is a fully calibrated rms-to-dc converter capable of
operating on signals of a few hertz to 2.7 GHz or more. Unlike
logarithmic amplifiers, the AD8364 response is waveform
independent. The device accurately measures waveforms that
have a high peak-to-rms ratio (crest factor). Figure 50 shows a
block diagram.
A single channel of the AD8364 consists of a high performance
AGC loop. As shown in Figure 51, the AGC loop comprises
a wide bandwidth variable gain amplifier (VGA), square law
detectors, an amplitude target circuit, and an output driver. For
a more detailed description of the functional blocks, see the
AD8362 data sheet.
OUTP = OUTA – OUTB + VLVL
OUTN = OUTB – OUTA + VLVL
(1)
(2)
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PWDN
COMR
CHP[A, B]
VST[A, B]
VPSA
VPSB
INH[A, B]
INL[A, B]
INHA
INHB
INLA
INLB
V
REF
25
26
27
28
29
30
31
32
V
V
V
2.5V
IN
ST[A, B]
REF
OFFSET
NULLING
REFERENCE
24
CHANNEL B
CHANNEL A
1
BAND GAP
TEMP
TruPwr™
TruPwr™
Figure 51. Single-Channel Details
VGA
23
2
OUTA
OUTB
BIAS
GSET
Figure 50. Block Diagram
SETPOINT
INTERFACE
22
3
EXTERNAL
V
CLP [A, B]
SIG
I
I
I
I
VGA
CONTROL
TGT
TGT
SIG
SIG
21
4
VGA
CONTROL
2
2
C
2
2
x
LPF
2
20
5
V
19
6
x
REF
C
2
F
× 0.03
18
7
COMPENSATION
TEMPERATURE
17
8
OUTPUT
BUFFER
16
15
14
13
12
11
10
9
VSTA
OUTA
FBKA
OUTP
OUTN
FBKB
OUTB
VSTB
ADJ[A, B]
OUT[A, B]
ACOM