ST95022 ST Microelectronics, ST95022 Datasheet

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ST95022

Manufacturer Part Number
ST95022
Description
2 Kbit Serial SPI EEPROM with High Speed Clock
Manufacturer
ST Microelectronics
Datasheet

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DESCRIPTION
The ST95022 is an high speed 2 Kbit Electrically
Erasable Programmable Memory (EEPROM) fab-
ricated with STMicroelectronics’s High Endurance
Single Polysilicon CMOS technology. The memory
is accessed by a simple SPI bus compatible serial
interface. The bus signals are a serial clock input
(C), a serial data input (D) and a serial data output
(Q).
Table 1. Signal Names
February 1999
HIGH SPEED CLOCK RATE:
– 2.1 MHz Max
1,000,000 ERASE/WRITE CYCLES
40 YEARS DATA RETENTION
SINGLE 4.5V to 5.5V SUPPLY VOLTAGE
SPI BUS COMPATIBLE SERIAL INTERFACE
BLOCK WRITE PROTECTION
STATUS REGISTER
16 BYTE PAGE MODE
WRITE PROTECT
SELF-TIMED PROGRAMMING CYCLE
E.S.D.PROTECTION GREATER than 4000V
SUPPORTS POSITIVE CLOCK SPI MODES
C
D
Q
S
W
HOLD
V
V
CC
SS
Serial Clock
Serial Data Input
Serial Data Output
Chip Select
Write Protect
Hold
Supply Voltage
Ground
2 Kbit Serial SPI EEPROM with High Speed Clock
Figure 1. Logic Diagram
HOLD
W
D
C
S
V CC
150mil Width
V SS
ST95022
8
SO8 (M)
1
ST95022
Q
AI01722
1/16

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ST95022 Summary of contents

Page 1

... SELF-TIMED PROGRAMMING CYCLE E.S.D.PROTECTION GREATER than 4000V SUPPORTS POSITIVE CLOCK SPI MODES DESCRIPTION The ST95022 is an high speed 2 Kbit Electrically Erasable Programmable Memory (EEPROM) fab- ricated with STMicroelectronics’s High Endurance Single Polysilicon CMOS technology. The memory is accessed by a simple SPI bus compatible serial interface ...

Page 2

... D output pin is at high imped- ance and, unless an internal write operation is underway the ST95022 will be in the standby power mode. S low enables the ST95022, placing it in the active power mode. It should be noted that after power-on, a high to low transition required prior to the start of any operation ...

Page 3

... HOLD is brought high while C is low. During the Hold condition D, Q, and C are at a high impedance state. When the ST95022 is under the Hold condition possible to deselect the device. However, the serial communications will remain paused after a reselect, and the chip will be reset. ...

Page 4

... RDSR WRSR READ WRITE Notes Upper page selected Lower page selected 4/16 out, the ST95022 enters a wait mode (data not decoded Hi-Z) until it is deselected. The status register format is as follows BP1, BP0: Read and write bits. WEL, WIP: Read only bits. ...

Page 5

... High Voltage Generator I/O Shift Register Data Register 16 Bytes X Decoder Table 4. Write Protected Block Size Status Register Bits BP1 ST95022 Status Block Protect AI01272 Array Protected Addresses Block Protected BP0 0 none none 1 C0h - FFh ...

Page 6

... WREN instruction byte is issued. Then the product is de- selected by taking S high. After the WREN instruc- tion byte is sent, the ST95022 will set the write enable latch and then remain in standby until it is deselected. Then the write state is entered by selecting the chip, issuing two bytes of instruction and address, and one byte of data ...

Page 7

... Figure 8. Byte Write Operation Sequence INSTRUCTION D HIGH IMPEDANCE HIGH IMPEDANCE BYTE ADDRESS AI01441 DATA BYTE AI01559 ST95022 7/16 ...

Page 8

... ST95022 Figure 9. Page Write Operation Sequence INSTRUCTION DATA BYTE Figure 10. RDSR: Read Status Register Sequence 8/ BYTE ADDRESS DATA BYTE N ...

Page 9

... The programming cy- cle will only start if the S transition occurs just after the eighth bit of data of a word is received. POWER ON STATE After a Power up the ST95022 is in the following state: – The device is in the low power standby state. – The chip is deselected. ...

Page 10

... ST95022 Table 5. AC Measurement Conditions Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Reference Voltages Output Load Note that Output Hi-Z is defined as the point where data is no longer driven. (1) Table 6. Input Parameters Symbol C Input Capacitance ( Input Capacitance (other pins) ...

Page 11

... HOLD High to Output Low-Z HHQX HOLD Low to Output High-Z HLQZ Write Cycle Time W WP Notes 1/ Value guaranteed by characterization, not 100% tested in production. Parameter Test Condition ST95022 Min Max Unit D.C. 2.1 MHz 100 ns 100 ns 190 ns 190 ...

Page 12

... ST95022 Figure 13. Serial Input Timing S tCHSL C tDVCH D HIGH IMPEDANCE Q Figure 14. Hold Timing HOLD 12/16 tSLCH tCHSH tCHDX tCLCH MSB IN tDLDH tDHDL tHLCH tCLHL tHLQZ tSHSL tSHCH tCHCL LSB IN AI01447 tHHCH tCLHH tHHQX AI01448 ...

Page 13

... Figure 15. Output Timing S C tCLQX Q ADDR.LSB IN D Figure 16. EEPROM and SPI Bus MASTER CS3 CS2 CS1 tCH tCLQV tQLQH tQHQL ST95xxx ST95xxx S S ST95022 tCL tSHQZ LSB OUT AI01449B ST95xxx S AI01446 13/16 ...

Page 14

... Note: 1. Data In is strobed on rising edge of the clock (C) and Data Out is synchronized from the falling edge of the clock. Devices are shipped from the factory with the memory content set at all "1’s" (FFh). For a list of available options (Package, etc...) or for further information on any aspect of this device, please contact the STMicroelectronics Sales Office nearest to you. 14/16 ST95022 Package ...

Page 15

... Drawing is not to scale. mm Min Max 1.35 1.75 0.10 0.25 0.33 0.51 0.19 0.25 4.80 5.00 3.80 4.00 – – 5.80 6.20 0.25 0.50 0. ST95022 inches Typ Min 0.053 0.069 0.004 0.010 0.013 0.020 0.007 0.010 0.189 0.197 0.150 0.157 0.050 – 0.228 0.244 0.010 0.020 0.016 0.035 0 8 0.004 h x 45˚ Max – ...

Page 16

... ST95022 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice ...

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