ST62T40B STMicroelectronics, ST62T40B Datasheet
ST62T40B
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ST62T40B Summary of contents
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... System (connects to an MS-DOS PC via a parallel port). DEVICE SUMMARY OTP DEVICE (Bytes) ST62T40B 7948 ST62E40B August 1999 8-BIT OTP/EPROM MCU WITH LCD DRIVER, EEPROM AND A/D CONVERTER with 7-bit (See end of Datasheet for Ordering Information) EPROM I/O Pins (Bytes 7948 ST62T40B/E40B PQFP80 CQFP80W Rev. 2.6 1/72 1 ...
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... ST62T40B/E40B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.2 PIN DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.3 MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.3.2 Program Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.3.3 Data Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 www.DataSheet4U.com 1.3.4 Stack Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.3.5 Data Window Register (DWR 1.3.6 Data RAM/EEPROM Bank Register (DRBR 1.3.7 EEPROM Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1.4 PROGRAMMING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 1.4.1 Option Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 1.4.2 Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 1.4.3 EEPROM Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 1.4.4 EPROM Erasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2 ...
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LCD alternate functions (combiports ...
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ST6240B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... EPROM/OTP versions only) PP common core is surrounded by a number of on- chip peripherals. The ST62E40B is the erasable EPROM version of the ST62T40B device, which may be used to em- ulate the ST62T40B device, as well as the respec- tive ST6240B ROM devices. 8-BIT A/D CONVERTER DATA ROM USER SELECTABLE ...
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... ST62T40B/E40B INTRODUCTION (Cont’d) OTP and EPROM devices are functionally identi- cal. The ROM based versions offer the same func- tionality selecting as ROM options the options de- fined in the programmable option byte of the OTP/EPROM versions.OTP devices offer all the advantages of user programmability at low cost, ...
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... A low level selects the hardware activated watchdog, while a high level selects the software activated watchdog for low consumption modes. This pin overcomes the option byte content. How- ever if WDON pin state is different from option byte content, extra consumption must be expected. ST62T40B/E40B 7/72 7 ...
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... ST62T40B/E40B 1.3 MEMORY MAP 1.3.1 Introduction The MCU operates in three separate memory spaces: Program space, Data space, and Stack space. Operation in these three memory spaces is described in the following paragraphs. Briefly, Program space contains user program code in Program memory and user vectors; Data space contains user data in RAM and in Program memory, and Stack space accommodates six lev- www ...
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... U.V. erasure that also results into the whole EPROM context erasure. Note: Once the Readout Protection is activated longer possible, even for STMicroelectronics, to gain access to the Program memory contents. Returned parts with a protection set can therefore not be accepted. ST62T40B/E40B PRPR1 PRPR0 PC bit 11 ...
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... Program memory. 1.3.3.2 Data RAM/EEPROM In ST62T40B and ST62E40B devices, the data space includes 60 bytes of RAM, the accumulator (A), the indirect registers (X), (Y), the short direct registers (V), (W), the I/O port registers, the pe- ...
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... ST62T40B/E40B DWR5 DWR4 DWR3 DWR2 DWR1 DWR0 PROGRAM SPACE ADDRESS READ DATA SPACE ADDRESS 40h-7Fh IN INSTRUCTION DATA SPACE ADDRESS 59h ...
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... DRBR is not affected. In DRBR Register, only 1 bit must be set. Other- wise two or more pages are enabled in parallel, producing errors. Table 6. Data RAM Bank Register Set-up DRBR 00h 01h 02h 08h 10h other ST62T40B/E40B None EEPROM Page 0 EEPROM Page 1 RAM Page 1 RAM Page 2 Reserved ...
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... The image register must be written to first so that interrupt oc- curs between the two instructions, the EECTL will not be affected The number of available 64-byte banks ( device dependent. ST62T40B/E40B Dataspace addresses. Banks 0 and 38h-3Fh 30h-37h ...
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... ST62T40B/E40B MEMORY MAP (Cont’d) Additional Notes on Parallel Mode: If the user wishes to perform parallel program- ming, the first step should be to set the E2PAR2 bit. From this time on, the EEPROM will be ad- dressed in write mode, the ROW address will be latched and it will be possible to change it only at the end of the programming cycle resetting E2PAR2 without programming the EEPROM ...
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... PC menu (PC driven Mode) or automatically (stand-alone mode) 1.4.2 Program Memory EPROM/OTP programming mode is set by a +12.5V voltage applied to the TEST/V programming flow of the ST62T40B/E40B is de- scribed in the User Manual of the EPROM Pro- gramming Board. The MCUs can be programmed with the ST62E4xB EPROM programming tools available from STMicroelectronics ...
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... ST62T40B/E40B 2 CENTRAL PROCESSING UNIT 2.1 INTRODUCTION The CPU Core of ST6 devices is independent of the I/O or Memory configuration. As such, it may be thought independent central processor communicating with on-chip I/O, Memory and Pe- ripherals via internal address, data, and control buses. In-core communication is arranged as shown in Figure 6; the controller being externally www ...
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... Switching between the three sets of flags is per- formed automatically when an NMI, an interrupt or a RETI instructions occurs. As the NMI mode is ST62T40B/E40B automatically selected after the reset of the MCU, the ST6 core uses at first the NMI flags. Stack. The ST6 CPU includes a true LIFO hard- ware stack which eliminates the need for a stack pointer ...
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... ST62T40B/E40B 3 CLOCKS, RESET, INTERRUPTS AND POWER SAVING MODES 3.1 CLOCK SYSTEM 3.1.1 Main Oscillator The MCU features a Main Oscillator which can be driven by an external clock, or used in conjunction with an AT-cut parallel resonant crystal or a suita- ble ceramic resonator. Figure 8 illustrates various possible oscillator con- www ...
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... Start/Stop bit in the oscillator status/control register. OSC32KHz OSC32KHz f /13 INT START EOSCI OSCEOC X STOP INT ST62T40B/E40B 7 S 500ms elapsed time (providing /13 MUX DIV 2 ...
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... ST62T40B/E40B 3.2 RESETS The MCU can be reset in three ways: – by the external Reset input being pulled low; – by Power-on Reset; – by the digital Watchdog peripheral timing out. 3.2.1 RESET Input The RESET pin may be connected to a device of the application board in order to reset the MCU if required ...
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... Figure 12. Reset and Interrupt Processing and DD rises OSC 300k 2.8k POWER ON RESET WATCHDOG RESET ST62T40B/E40B RESET JP:2 BYTES/4 CYCLES JP RESET VECTOR INITIALIZATION ROUTINE RETI: 1 BYTE/2 CYCLES RETI ST6 CK INTERNA L RESET COUNTER RESET RESET VA00181 ...
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... ST62T40B/E40B RESETS (Cont’d) Table 8. Register Reset Status Register EEPROM Control Register Port Data Registers Port A,B Direction Register Port A,B Option Register Interrupt Option Register www.DataSheet4U.com SPI Registers LCD Mode Control Register 32kHz Oscillator Register Port C Direction Register Port C Option Register Register ...
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... The STOP instruction is interpreted as a WAIT instruc- tion, and the Watchdog continues to countdown. When the MCU exits STOP mode (i.e. when an in- terrupt is generated), the Watchdog resumes its activity. Stop Mode Watchdog ST62T40B/E40B Recommended Options “SOFTWARE WATCHDOG” “HARDWARE WATCHDOG” 23/72 23 ...
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... ST62T40B/E40B DIGITAL WATCHDOG (Cont’d) The Watchdog is associated with a Data space register (Digital WatchDog Register, DWDR, loca- tion 0D8h) which is described in greater detail in Section 3.3.1 Digital Watchdog Register (DWDR). This register is set to 0FEh on Reset: bit C is cleared to “0”, which disables the Watchdog; the timer downcounter bits T5, and the SR bit are all set to “ ...
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... The software activation option should be chosen only when the Watchdog counter used as a timer. To ensure the Watchdog has not been un- expectedly activated, the following instructions should be executed within the first 27 instructions: jrr 0, WD, #+3 ST62T40B/E40B 25/72 25 ...
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... ST62T40B/E40B DIGITAL WATCHDOG (Cont’d) These instructions test the C bit and Reset the MCU (i.e. disable the Watchdog) if the bit is set (i.e. if the Watchdog is active), thus disabling the Watchdog. In all modes, a minimum of 28 instructions are ex- ecuted after activation, before the Watchdog can generate a Reset. Consequently, user software Figure 15 ...
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... Table 11. Interrupt Option Register Description 3 (FF4h-FF5h) 4 (FF2h-FF3h) GEN 5 (FF0h-FF1h) ESB LES OTHERS ST62T40B/E40B SET Enable all interrupts CLEARED Disable all interrupts Rising edge mode on inter- SET rupt source #2 Falling edge mode on inter- CLEARED rupt source #2 Level-sensitive mode on in- SET terrupt source #1 ...
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... ST62T40B/E40B INTERRUPTS (Cont’d) 3.4.2 Interrupt Procedure The interrupt procedure is very similar to a call pro- cedure, indeed the user can consider the interrupt as an asynchronous call procedure. As this is an asynchronous event, the user cannot know the context and the time at which it occurred re- sult, the user should save all Data space registers which may be used within the interrupt routines ...
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... ETI D7h D1h EAI C2h ALL C0h-C4h ORPAn-DRPAn C1h-C5h ORPBn-DRPBn C6h-CFh ORPCn-DRPCn DAh PEI DBh EOSCI ST62T40B/E40B sources available on Interrupt Masked Interrupt Source source All Interrupts, excluding NM I All TMZ: TIMER Overflow source 3 EOC: End of Conversion source 4 End of Transmission source 1 PAn pin ...
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... ST62T40B/E40B INTERRUPTS (Cont’d) Figure 17. Interrupt Block Diagram www.DataSheet4U.com NMI FROM REGISTER PORT A,B,C SINGLE BIT ENABLE PBE V DD PORT A PBE PORT B PORT C PBE Bits 30/72 30 PIF PSS PEI CLK FF SPI CLK Q CLR I 1 CLK IOR bit 5 (ESB) TMZ TIMER1 ETI TMZ TIMER2 ...
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... Watchdog), the MCU enters a normal reset proce- dure interrupt is generated during WAIT mode, the MCU’s behaviour depends on the state ST62T40B/E40B of the processor core prior to the WAIT instruction, but also on the kind of interrupt request which is generated. This is described in the following para- graphs ...
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... ST62T40B/E40B POWER SAVING MODE (Cont’d) 3.5.3 Exit from WAIT and STOP Modes The following paragraphs describe how the MCU exits from WAIT and STOP modes, when an inter- rupt occurs (not a Reset). It should be noted that the restart sequence depends on the original state ...
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... During MCU initialization, all I/O reg- isters are cleared and the input mode with pull-ups and no interrupt generation is selected for all the pins, thus avoiding pin conflicts. RESET DATA DIRECTION REGISTE R DATA REGISTE R OPTION REGISTE R ST62T40B/E40B INPUT /OUTPUT VA00413 33/72 33 ...
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... ST62T40B/E40B I/O PORTS (Cont’d) 4.1.1 Operating Modes Each pin may be individually programmed as input or output with various configurations. This is achieved by writing the relevant bit in the Data (DR), Data Direction (DDR) and Option reg- isters (OR). Table 13 illustrates the various port configurations which can be selected by user soft- ware ...
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... Interrupt 010* pull-up Input pull-up (Reset 000 state) Output 100 Open Drain Output 110 Push-pull ST62T40B/E40B Input 011 Analog Input 001 Output 101 Open Drain Output 111 Push-pull 35/72 35 ...
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... ST62T40B/E40B I/O PORTS (Cont’d) Table 14. I/O Port configuration for the ST62T40B/E40B MODE Input www.DataSheet4U.com Input with pull up (Reset state except for PC0-PC7) Input with pull up with interrupt Analog Input Open drain output 5mA Open drain output 20mA Push-pull output 5mA Push-pull output 20mA Note 1 ...
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... DR Mode 0 Input With pull-up, no interrupt 1 Input No pull-up, no interrupt 0 Input With pull-up and with interrupt 1 Input LCD segment (Reset state) X Output Open-drain output X Output Push-pull output PID PP/OD OPR 1 DR MUX 0 PID DR PID DR ST62T40B/E40B Optio n OUT IN SYNCHRONOUS SERIAL I/O CLOCK VR01661F 37/72 37 ...
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... ST62T40B/E40B I/O PORTS (Cont’d) 4.1.5 I/O Port Option Registers ORA/B/C (CCh PA, CDh PB, CFh PC) Read/Write 7 Px7 Px6 Px5 Px4 Bit 7-0 = Px7 - Px0: Port Option Register bits. www.DataSheet4U.com 4.1.6 I/O Port Data Direction Registers DDRA/B/C (C4h PA, C5h PB, C6h PC) Read/Write 7 Px7 Px6 Px5 Px4 Bit 7-0 = Px7 - Px0: Port Data Direction Registers bits ...
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... PS2/PS1/PS0 bits in the control register. Figure 21 illustrates the Timer’s working principle. 7-BIT PRESCALER BIT1 BIT2 BIT3 8-1 MULTIPLEXER BIT1 BIT2 BIT3 BIT4 8-BIT COUNTER ST62T40B/E40B divided by 12 (TIMER 1 & ex- INT BIT4 BIT5 BIT6 PS0 PS1 PS2 BIT7 BIT5 BIT6 VA00186 ...
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... ST62T40B/E40B Figure 22. TIMER 1 Block Diagram PSC www.DataSheet4U.com TIMER Figure 23. TIMER 2 Block Diagram f INT 12 40/72 40 DATABUS COUNTER 4 SELECT SYNCHRONIZATION LOGIC DATA BUS 8 6 8-BIT 5 COUNTER 4 SELECT PSC 8-BIT ...
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... TMZ bit is not set until the 8-bit counter reaches 00h again. The values of the TCR and the PSC registers can be read accurately at any time. Timer Function Event Counter Gated Input Output “0” Output “1” ST62T40B/E40B 12). INT 41/72 41 ...
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... ST62T40B/E40B TIMER 1& 2 (Cont’d) 4.2.5 TIMER 1 Registers Timer Status Control Register (TSCR) Address: 0D4h — Read/Write 7 TMZ ETI TOUT DOUT Bit 7 = TMZ: Timer Zero bit www.DataSheet4U.com A low-to-high transition indicates that the timer count register has decrement to zero. This bit must be cleared by user software before starting a new count ...
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... D4 PSI PS2 PS1 PS0 Timer Counter Register (TCR) Address: 0D6h — Read/Write Bit 7-0 = D7-D0: Counter Bits. Prescaler Register PSC Address: 0D5h — Read/Write Bit 7 = D7: Always read as ”0”. Bit 6-0 = D6-D0: Prescaler Bits. ST62T40B/E40B PS2 PS1 PS0 ...
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... ST62T40B/E40B 4.3 A/D CONVERTER (ADC) The A/D converter peripheral is an 8-bit analog to digital converter with analog inputs as alternate I/O functions (the number of which is device depend- ent), offering 8-bit resolution with a typical conver- sion time of 70us (at an oscillator clock frequency of 8MHz). The ADC converts the input voltage by a process ...
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... A/D converter if set to “1”. Writing a “0” to this bit will put the ADC in power down mode (idle mode). Bit 3-0 = D3-D0. Not used DD A/D Converter Data Register (ADR) Address: 0D0h — Read only Bit 7-0 = D7- Bit A/D Conversion Result. ST62T40B/E40B 7 EOC STA PDS ...
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... ST62T40B/E40B 4.4 SERIAL PERIPHERAL INTERFACE (SPI) The on-chip SPI is an optimized serial synchro- nous interface that supports a wide range of indus- try standard SPI specifications. The on-chip SPI is controlled by small and simple user software to perform serial data exchange. The serial shift clock can be implemented either by software (us- ...
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... SCL clock frequency by simply putting the SCL I/O line in output open-drain mode and writing a zero into the corresponding data register bit. ST62T40B/E40B possible to directly read the Sin pin directly through the port register, the software can detect a difference between internal data and external data (master mode) ...
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... ST62T40B/E40B 4.5 LCD CONTROLLER-DRIVER On-chip LCD driver includes all features required for LCD driving, including multiplexing of the com- mon plates. Multiplexing allows to increase display capability without increasing the number of seg- ment outputs. In that case, the display capability is equal to the product of the number of common plates with the number of segment outputs ...
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... Reserved Note: For display voltages V tivity of the divider may be too high for some appli- cations (especially using 1/3 or 1/4 duty display mode). In that case an external resistive divider must be used to achieve the desired resistivity. ST62T40B/E40B LCDOFF V LCD LCD2 ...
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... ST62T40B/E40B LCD CONTROLLER-DRIVER (Continued) Figure 29. Typical Network to connect to V pins if V 4.5V LCD V LCD V LCD2/3 www.DataSheet4U.com V LCD1 Figure 30. Addressing Map of the LCD RAM RAM Address 50/72 50 Typical External resistances values are in the LCD range of 100 K to 150 K ...
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... LF0, LF1, LF2 define the 32KHz division factor as shown in Table 23. Table 23. 32KHz Division Factor for Base Frequency Selection Division Factor LF2 LF1 INT ST62T40B/E40B DS0 HF2 HF1 HF0 LF2 LF1 LF0 32KHz Division Factor 0 0 512 0 1 386 1 ...
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... ST62T40B/E40B 4.6 POWERSUPPLY SUPERVISOR DEVICE (PSS) The Power Supply Supervisor device, described in the Figure 32, permits supervising the crossing of the PSS pin voltage (VPSS) through a program- mable voltage (mxV chosen by software. This device includes: – An internal comparator which is connected to the internal INT line to make an interrupt request to the Core. – ...
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... DD /13 voltage. The n and DD m --- - n The PIF bit is the interrupt request flag of the PSS device. This bit follows PSS comparator output. L48xx ST62T40B/E40B /13 at detection < V -2V PSS DD /13 at detection < ...
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... ST62T40B/E40B POWER SUPPLY SUPERVISOR (Continued) 4.6.2 PSS Register The PSS register permits control over the PSS de- vice. The register can be addressed in the data space as a RAM location at DAh. This register is cleared after Reset. PSS Status Control Register (PSSCR) Address: DAh - Read/Write 7 www.DataSheet4U.com ...
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... Extended. In the extended addressing mode, the 12-bit address needed to define the instruction is obtained by concatenating the four less significant ST62T40B/E40B bits of the opcode with the byte following the op- code. The instructions (JP, CALL) which use the extended addressing mode are able to branch to any address of the 4K bytes Program space ...
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... ST62T40B/E40B 5.3 INSTRUCTION SET The ST6 core offers a set of 40 basic instructions which, when combined with nine addressing modes, yield 244 usable opcodes. They can be di- vided into six different types: load/store, arithme- tic/logic, conditional branch, control instructions, jump/call, and bit manipulation. The following par- agraphs describe the different types ...
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... Short Direct 1 Short Direct 1 Direct 2 Direct 2 Indirect 1 Indirect 1 Short Direct 1 Short Direct 1 Short Direct 1 Short Direct 1 Direct 2 Direct 2 Indirect 1 Indirect 1 Inherent 1 Inherent 2 Indirect 1 Indirect 1 Direct 2 Immediate 2 ST62T40B/E40B Flags Cycles ...
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... ST62T40B/E40B INSTRUCTION SET (Cont’d) Conditional Branch. The branch instructions achieve a branch in the program when the select- ed condition is met. Bit Manipulation Instructions. These instruc- tions can handle any bit in data space memory. One group either sets or clears. The other group (see Conditional Branch) performs the bit test branch operations ...
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... Indicates Ill egal Instructions e 5 Bit Displacement b 3 Bit Address rr 1byte dataspace address nn 1 byte immediate data abc 12 bit address ee 8 bit Displacement ST62T40B/E40B LOW 0101 0110 0111 JRZ 2 JRC a,(x) pcr 1 prc 1 ind JRZ 4 INC 2 ...
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... ST62T40B/E40B Opcode Map Summary (Continued) LOW 8 1000 HI 2 JRNZ 0000 1 pcr 2 2 JRNZ 0001 1 pcr 2 2 JRNZ www.DataSheet4U.com 0010 1 pcr 2 2 JRNZ 0011 1 pcr 2 2 JRNZ 0100 1 pcr 2 2 JRNZ 0101 1 pcr 2 2 JRNZ ...
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... Where and lower than Parameter , (source) DD (sink) SS ST62T40B/E40B Tj RthJA Ambient Temperature. RthJA = Package thermal resistance (junction-to ambient Pint + Pport. Pint = IDD x VDD (chip internal power). Pport = Port power dissipation (deter- mined by the user). Value Unit -0.3 to 7.0 ...
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... ST62T40B/E40B 6.2 RECOMMENDED OPERATING CONDITIONS Symbol Parameter T Operating Temperature A V Operating Supply Voltage DD f Oscillator Frequency OSC www.DataSheet4U.com I Pin Injection Current (positive) INJ+ I Pin Injection Current (negative) V INJ- Notes: 1. Care must be taken in case of negative current injection, where adapted impedance must be respected on analog sources to not affect the A/D conversion ...
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... RESET SS f =8MHz OSC V =5.0V f =8MHz (2) DD INT V =5.0V f =8MHz DD INT I =0mA LOAD V =5.0V DD ST62T40B/E40B Value Unit Min. Typ. Max 0 0 0.2 V 0.2 0.1 0.8 V 0.1 0.8 1.3 4.9 V 3.5 40 100 200 150 350 900 0.1 1 -16 - ...
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... ST62T40B/E40B 6.4 AC ELECTRICAL CHARACTERISTICS (T = -40 to +85 C unless otherwise specified) A Symbol t Supply Recovery Time REC Minimum Pulse Width (V T RESET pin WR NMI pin T EEPROM Write Time www.DataSheet4U.com WEE Endurance EEPROM WRITE/ERASE Cycle Retention EEPROM Data Retention C Input Capacitance IN C Output Capacitance OUT Notes: 1 ...
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... Test Conditio ns DC Offset Voltage V = Vdd, no load LCD I=100 I=100 Display Voltage See Note 2 Parameter Test Conditio ns V =5.0V, T PSS PSS Running PSS Stopped ST62T40B/E40B Value Min. Typ. Max. f INT --------- - 8 1 125 Value Min. Typ. Max 100 Value Min ...
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... ST62T40B/E40B 7 GENERAL INFORMATION 7.1 PACKAGE MECHANICAL DATA Figure 35. 80-Pin Plastic Quad Flat Package www.DataSheet4U.com Figure 36. 80-Pin Ceramic Quad Flat Package 66/72 66 Dim Min A A1 0.25 A2 2.55 2.80 3.05 0.100 0.110 0.120 B 0.30 C 0.13 D 22.95 23.20 23.45 0.904 0.913 0.923 D1 19.90 20.00 20.10 0.783 0.787 0.791 D3 E 16.95 17.20 17.45 0.667 0.677 0.687 E1 13.90 14.00 14.10 0.547 0.551 0.555 ...
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... INFORMATION www.DataSheet4U.com Table 32. OTP/EPROM VERSION ORDERING INFORMATION Sales Type ST62E40BG1 ST62T40BQ6 Parameter Test Conditions PQFP80 CQFP80W Program I/O Memory (Bytes) 7948 (EPROM 7948 (OTP) ST62T40B/E40B Value Unit Min. Typ. Max Temperature Range Package CQFP80W - PQFP80 C/W 67/72 ...
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... ST62T40B/E40B Notes: www.DataSheet4U.com 68/72 68 ...
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Supply Operating Range 8 MHz Maximum Clock Frequency www.DataSheet4U.com -40 to +85 C Operating Temperature Range Run, Wait and Stop Modes 5 Interrupt Vectors Look-up Table capability in Program Memory Data Storage in Program Memory: User selectable ...
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... ST6240B 1 GENERAL DESCRIPTION 1.1 INTRODUCTION The ST6240B is mask programmed ROM version of ST62T40B OTP devices. They offer the same functionality as OTP devices, selecting as ROM options the options defined in the programmable option byte of the OTP version. Figure 1. Programming wave form www.DataSheet4U.com TEST 15 14V typ ...
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... Customer Address Contact Phone No www.DataSheet4U.com Reference STMicroelectronics references Device: Package: Temperature Range: Special Marking: Authorized characters are letters, digits, ’.’, ’-’, ’/’ and spaces only. Maximum character count: Watchdog Selection: NMI Pull-Up Selection: Timer Pull-Up Selection: ROM Readout Protection: ...
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... No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without the express written approval of STMicroelectronics ...