ST62T42B ST Microelectronics, ST62T42B Datasheet - Page 41
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ST62T42B
Manufacturer Part Number
ST62T42B
Description
8-BIT OTP/EPROM MCU WITH LCD DRIVER / EEPROM AND A/D CONVERTER
Manufacturer
ST Microelectronics
Datasheet
1.ST62T42B.pdf
(68 pages)
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TIMER 1& 2 (Cont’d)
5.1.4 TIMER 1 Registers
Timer Status Control Register (TSCR)
Address: 0D4h — Read/Write
Bit 7 = TMZ: Timer Zero bit
A low-to-high transition indicates that the timer
count register has decrement to zero. This bit
must be cleared by user software before starting a
new count.
Bit 6 = ETI: Enable Timer Interrup
When set, enables the timer interrupt request. If
ETI=0 the timer interrupt is disabled. If ETI=1 and
TMZ=1 an interrupt request is generated.
Bit 5 = Reserved. Must be set to 1.
Bit 4 = Do not care
Data sent to the timer output when TMZ is set high
(output mode only). Input mode selection (input
mode only)
Bit 3 = PSI: Prescaler Initialize Bit
Used to initialize the prescaler and inhibit its count-
ing. When PSI=“0” the prescaler is set to 7Fh and
the counter is inhibited. When PSI=“1” the prescal-
er is enabled to count downwards. As long as
PSI=“0” both counter and prescaler are not run-
ning.
Bit 2, 1, 0 = PS2, PS1, PS0: Prescaler Mux. Se-
lect. These bits select the division ratio of the pres-
caler register.
TMZ
7
ETI
-
-
PSI
PS2
PS1
PS0
0
Timer Counter Register (TCR)
Address: 0D3h — Read/Write
Bit 7-0 = D7-D0: Counter Bits.
Prescaler Register PSC
Address: 0D2h — Read/Write
Bit 7 = D7: Always read as ”0”.
Bit 6-0 = D6-D0: Prescaler Bits.
D7
D7
7
7
PS2
0
0
0
0
1
1
1
1
D6
D6
D5
D5
PS1
1
0
0
1
1
0
0
1
D4
D4
D3
D3
ST62T42B/E42B
PS0
1
0
1
0
1
0
1
0
D2
D2
Divided by
D1
D1
128
16
32
64
8
1
2
4
41/68
D0
D0
0
0
41