AD9248BST-65 Analog Devices, Inc., AD9248BST-65 Datasheet - Page 18

• Manufacturer Part Number: AD9248BST-65
• Description: 14-bit, 20/40/65 Msps Dual A/ D Converter
• Manufacturer: Analog Devices, Inc.

AD9248
The data format can be selected for either offset binary or twos
complement. This is discussed later in the Data Format section.
TIMING
The AD9248 provides latched data outputs with a pipeline
delay of seven clock cycles. Data outputs are available one
propagation delay (t
Refer to Figure 2 for a detailed timing diagram.
The internal duty cycle stabilizer can be enabled on the
DATA FORMAT
The AD9248 data output format can be configured for either
twos complement or offset binary. This is controlled by the
Data Format Select pin (DFS). Connecting DFS to AGND will
produce offset binary output data. Conversely, connecting DFS
to AVDD will format the output data as twos complement.
The output data from the dual A/D converters can be
multiplexed onto a single 12-bit output bus. The multiplexing is
accomplished by toggling the MUX_SELECT bit, which
directs channel data to the same or opposite channel data port.
When MUX_SELECT is logic high, the Channel A data is
directed to Channel A output bus, and Channel B data is
directed to the Channel B output bus. When MUX_SELECT is
logic low, the channel data is reversed, i.e., Channel A data is
directed to the Channel B output bus and Channel B data is
directed to the Channel A output bus. By toggling the
MUX_SELECT bit, multiplexed data is available on either of
the output data ports.
If the ADCs are run with synchronized timing, this same clock
can be applied to the MUX_SELECT bit. After the
MUX_SELECT rising edge, either data port will have the data
for its respective channel; after the falling edge, the alternate
channel’s data will be placed on the bus. Typically, the other
unused bus would be disabled by setting the appropriate OEB
high to reduce power consumption and noise. Figure xx shows
an example of multiplex mode. When multiplexing data, the
data rate is two times the sample rate. Note that both channels
must remain active in this mode and that each channel's power-
Figure xx. Example of Multiplexed Data Format Using the Channel A Output and the Same Clock Tied to CLK_A, CLK_B, and MUX_SELECT
PD
) after the rising edge of the clock signal.
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AD9248-65 using the DCS pin. This provides a stable 50%
duty cycle to internal circuits.
The length of the output data lines and loads placed on them
should be minimized to reduce transients within the AD9248.
These transients can detract from the converter’s dynamic
performance. The lowest typical conversion rate of the AD9248
is 1 MSPS. At clock rates below 1 MSPS, dynamic
performance may degrade.
down pin must remain low.
Preliminary Technical Data