TS68040MR25A Atmel Corporation, TS68040MR25A Datasheet - Page 20

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TS68040MR25A

Manufacturer Part Number
TS68040MR25A
Description
Manufacturer
Atmel Corporation
Datasheet
Table 14. Output AC Timing Specifications
These output specifications are only for 25 MHz. They must be scaled for lower operating frequencies. Refer to
TS6804DH/AD for further information. -55°C T
20
Num
11
12
13
14
18
19
20
21
26
27
28
29
30
38
39
40
43
48
50
Characteristic
BCLK to address CIOUT, LOCK, LOCKE,
R/W, SIZn, TLN, TMn, UPAn valid
BCLK to output invalid (output hold)
BCLK to TS valid
BCLK to TIP valid
BCLK to data-out valid
BCLK to data-out invalid (output hold)
BCLK to output low impedance
BCLK to data-out high impedance
BCLK to multiplexed address valid
BCLK to multiplexed address driven
BCLK to multiplexed address high
impedance
BCLK to multiplexed data driven
BCLK to multiplexed data valid
BCLK to address CIOUT, LOCK, LOCKE,
R/W, SIZn, TS, TLNn, TMn, TTn, UPAn high
impedance
BCLK to BB, TA, TIP high impedance
BCLK to BR, BB valid
BCLK to MI valid
BCLK to TA valid
BCLK to IPEND, PSTn, RSTO valid
TS68040
(5)(6)
(5)
(6)
Figure 8. Clock Input Timing
(6)
(5)(6)
(6)
(5)
(5)
(5)
(6)
(1)
(Figure 9 to Figure 15)
C
T
Jmax
Min
; 4.75V V
19
19
19
19
19
9
9
9
9
9
9
9
9
9
9
9
9
9
9
Buffer
Large
Max
(1)
21
21
21
23
20
31
18
33
18
28
21
21
21
21
25 MHz
CC
5.25V unless otherwise specified.
Min
19
19
19
19
19
9
9
9
9
9
9
9
9
9
9
9
9
9
9
Buffer
Small
Max
(1)
30
28
30
30
30
32
20
40
18
42
18
30
30
30
6.50
6.50
6.50
6.50
6.50
6.50
6.50
6.50
6.50
6.50
6.50
6.50
6.50
6.50
Min
14
14
14
14
14
Buffer
Large
Max
(1)
18
18
18
20
17
26
15
20
28
15
23
18
18
18
18
33 MHz
6.50
6.50
6.50
6.50
6.50
6.50
6.50
6.50
6.50
6.50
6.50
6.50
6.50
6.50
Min
14
14
14
14
14
Buffer
(2)(3)(4)
Small
2116A–HIREL–09/02
Max
(1)
25
25
25
27
17
33
15
20
35
15
23
25
25
25
25
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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