74HC574D,653 NXP Semiconductors, 74HC574D,653 Datasheet - Page 8

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74HC574D,653

Manufacturer Part Number
74HC574D,653
Description
IC FLIP FLOP OCTAL D 3ST 20SOIC
Manufacturer
NXP Semiconductors
Series
74HCr
Type
D-Type Busr
Datasheet

Specifications of 74HC574D,653

Output Type
Tri-State Non Inverted
Package / Case
20-SOIC (7.5mm Width)
Function
Standard
Number Of Elements
1
Number Of Bits Per Element
8
Frequency - Clock
133MHz
Delay Time - Propagation
14ns
Trigger Type
Positive Edge
Voltage - Supply
2 V ~ 6 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Number Of Circuits
1
Logic Family
HC
Logic Type
D-Type Edge Triggered Flip-Flop
Polarity
Non-Inverting
Input Type
Single-Ended
Propagation Delay Time
14 ns at 5 V
High Level Output Current
- 7.8 mA
Low Level Output Current
7.8 mA
Supply Voltage (max)
6 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Supply Voltage (min)
2 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Current - Output High, Low
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-1479-2
74HC574D-T
933715520653
NXP Semiconductors
Table 7.
Voltages are referenced to GND (ground = 0 V); C
[1]
[2]
[3]
[4]
[5]
74HC_HCT574
Product data sheet
Symbol Parameter
C
For type 74HCT574
t
t
t
t
t
t
t
f
C
pd
en
dis
t
W
su
h
max
PD
PD
t
t
t
t
C
P
f
f
C
V
N = number of inputs switching;
(C
pd
en
dis
t
i
o
D
CC
PD
= input frequency in MHz;
L
is the same as t
= output frequency in MHz;
is the same as t
is the same as t
= output load capacitance in pF;
= C
is the same as t
L
is used to determine the dynamic power dissipation (P
= supply voltage in V;
 V
power
dissipation
capacitance
propagation
delay
enable time
disable time OE to Qn; see
transition
time
pulse width
set-up time
hold time
maximum
frequency
power
dissipation
capacitance
PD
Dynamic characteristics
CC
 V
2
 f
CC
o
2
) = sum of outputs.
 f
THL
PLH
PZH
PLZ
i
 N + (C
and t
Conditions
C
V
CP to Qn; see
OE to Qn; see
Qn; see
CP HIGH or LOW;
see
Dn to CP; see
Dn to CP; see
CP; see
C
V
and t
and t
and t
I
I
L
L
V
V
V
V
V
V
V
V
V
V
= GND to V
= GND to V
= 50 pF; f = 1 MHz;
= 50 pF; f = 1 MHz;
TLH
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
Figure 8
PHL
PZL
PHZ
.
= 4.5 V
= 5 V; C
= 4.5 V
= 4.5 V
= 4.5 V
= 4.5 V
= 4.5 V
= 4.5 V
= 4.5 V
= 5 V; C
L
.
.
.
Figure 7
Figure 7
 V
CC
2
…continued
CC
CC
Figure 8
Figure 8
Figure 7
Figure 9
Figure 9
L
L
 f
= 15 pF
= 15 pF
o
All information provided in this document is subject to legal disclaimers.
) where:
Rev. 3 — 15 December 2010
L
= 50 pF unless otherwise specified; for test circuit see
[5]
[1]
[2]
[3]
[4]
[5]
D
Min
in W).
16
12
30
5
-
-
-
-
-
-
-
-
Octal D-type flip-flop; positive edge-trigger; 3-state
25 C
Typ
22
18
15
19
16
1
69
76
25
5
7
3
Max
33
33
28
12
-
-
-
-
-
-
-
-
74HC574; 74HCT574
40 C to +85 C 40 C to +125 C Unit
Min
20
15
24
5
-
-
-
-
-
-
-
-
Max
41
41
35
15
-
-
-
-
-
-
-
-
Min
24
18
20
5
-
-
-
-
-
-
-
-
© NXP B.V. 2010. All rights reserved.
Figure
Max
50
50
42
18
-
-
-
-
-
-
-
-
10.
8 of 19
pF
ns
ns
ns
ns
ns
ns
ns
ns
MHz
MHz
pF

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