74VCX16374TTR STMicroelectronics, 74VCX16374TTR Datasheet

IC FLIP FLOP 16BIT LV D 48-TSSOP

74VCX16374TTR

Manufacturer Part Number
74VCX16374TTR
Description
IC FLIP FLOP 16BIT LV D 48-TSSOP
Manufacturer
STMicroelectronics
Series
74VCXr
Type
D-Type Busr
Datasheet

Specifications of 74VCX16374TTR

Function
Standard
Output Type
Tri-State Non Inverted
Number Of Elements
2
Number Of Bits Per Element
8
Frequency - Clock
235MHz
Delay Time - Propagation
1ns
Trigger Type
Positive Edge
Current - Output High, Low
24mA, 24mA
Voltage - Supply
1.8 V ~ 3.6 V
Operating Temperature
-55°C ~ 125°C
Mounting Type
Surface Mount
Package / Case
48-TSSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
497-1097-2
LOW VOLTAGE CMOS 16-BIT D-TYPE FLIP-FLOP (3-STATE)
DESCRIPTION
The 74VCX16374 is a low voltage CMOS 16 BIT
D-TYPE FLIP-FLOP with 3 STATE OUTPUTS
NON
silicon gate and five-layer metal wiring C
technology. It is ideal for low power and very high
speed 1.8 to 3.6V applications; it can be interfaced
to 3.6V signal environment for both inputs and
outputs.
These 16 bit D-TYPE flip-flops are controlled by
two clock inputs (nCK) and two output enable
inputs (nOE).
On the positive transition of the (nCK), the nQ
outputs will be set to the logic state that were
setup at the nD inputs.
While the (nOE) input is low, the 8 outputs (nQ)
will be in a normal state (HIGH or LOW logic level)
and while high level the outputs will be in a high
impedance state.
Any output control does not affect the internal
operation of flip flops; that is, the old data can be
retained or the new data can be entered even
while the outputs are off.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
February 2003
3.6V TOLERANT INPUTS AND OUTPUTS
HIGH SPEED :
t
t
t
POWER DOWN PROTECTION ON INPUTS
AND OUTPUTS
SYMMETRICAL OUTPUT IMPEDANCE:
|I
|I
|I
OPERATING VOLTAGE RANGE:
V
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 16374
LATCH-UP PERFORMANCE EXCEEDS
300mA (JESD 17)
ESD PERFORMANCE:
HBM > 2000V (MIL STD 883 method 3015);
MM > 200V
PD
PD
PD
OH
OH
OH
CC
= 3.0 ns (MAX.) at V
= 3.4 ns (MAX.) at V
= 6.8 ns (MAX.) at V
| = I
| = I
| = I
(OPR) = 1.8V to 3.6V
INVERTING fabricated with sub-micron
OL
OL
OL
= 24mA (MIN) at V
= 18mA (MIN) at V
= 6mA (MIN) at V
WITH 3.6V TOLERANT INPUTS AND OUTPUTS
CC
CC
CC
= 3.0 to 3.6V
= 2.3 to 2.7V
= 1.8V
CC
CC
CC
= 1.8V
= 3.0V
= 2.3V
2
MOS
ORDER CODES
PIN CONNECTION
PACKAGE
TSSOP
TSSOP
TUBE
74VCX16374
74VCX16374TTR
T & R
1/12

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74VCX16374TTR Summary of contents

Page 1

... All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. February 2003 = 3.0 to 3.6V = 2.3 to 2.7V = 1. 2.3V ORDER CODES CC = 1.8V CC PACKAGE TSSOP PIN CONNECTION 2 MOS 74VCX16374 TSSOP TUBE T & R 74VCX16374TTR 1/12 ...

Page 2

INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No SYMBOL NAME AND FUNCTION 1 1OE 3 State Output Enable Input (Active LOW 1Q0 to 1Q7 3-State Outputs 11, 12 13, 14, 16, 17, ...

Page 3

LOGIC DIAGRAM This logic diagram has not to be used to estimate propagation delays ABSOLUTE MAXIMUM RATINGS Symbol V Supply Voltage Input Voltage Output Voltage (OFF State Output Voltage (High or ...

Page 4

DC SPECIFICATIONS (2.7V < V Symbol Parameter V High Level Input IH Voltage V Low Level Input IL Voltage V High Level Output OH Voltage V Low Level Output OL Voltage I Input Leakage I Current I Power Off ...

Page 5

DC SPECIFICATIONS (2.3V < V Symbol Parameter V High Level Input IH Voltage V Low Level Input IL Voltage V High Level Output OH Voltage V Low Level Output OL Voltage I Input Leakage I Current I Power Off Leakage ...

Page 6

DYNAMIC SWITCHING CHARACTERISTICS (T Symbol Parameter V Dynamic Low Voltage Quiet OLP Output (note Dynamic Low Voltage Quiet OLV Output (note Dynamic High Voltage Quiet OHV Output (note Number of ...

Page 7

CAPACITIVE CHARACTERISTICS Symbol Parameter C Input Capacitance IN C Output Capacitance OUT C Power Dissipation Capacitance PD (note defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption ...

Page 8

WAVEFORM 1: nCK TO Qn PROPAGATION DELAYS, nCK MAXIMUM FREQUENCY nCK SETUP AND HOLD TIMES (f=1MHz; 50% duty cycle) WAVEFORM 2: OUTPUT ENABLE AND DISABLE TIME (f=1MHz; 50% duty cycle) 8/12 ...

Page 9

WAVEFORM 3 : nCK MINIMUM PULSE WIDTH (f=1MHz; 50% duty cycle) 74VCX16374 9/12 ...

Page 10

DIM. MIN 0. 0.17 c 0. 0˚ PIN 1 IDENTIFICATION 1 10/12 TSSOP48 MECHANICAL DATA mm. TYP MAX. 1.2 0.15 0.9 0.27 ...

Page 11

Tape & Reel TSSOP48 MECHANICAL DATA mm. DIM. MIN. TYP A C 12 8.7 Bo 13.1 Ko 1.5 Po 3.9 P 11.9 inch MAX. MIN. TYP. 330 13.2 0.504 0.795 2.362 30.4 8.9 0.343 ...

Page 12

... No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied ...

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