AD538 Analog Devices, AD538 Datasheet - Page 9

• Manufacturer Part Number: AD538
• Description: Real-Time Analog Computational Unit ACU
• Manufacturer: Analog Devices

ANALOG COMPUTATION OF POWERS AND ROOTS
It is often necessary to raise the quotient of two input signals to
a power or take a root. This could be squaring, cubing, square-
rooting or exponentiation to some noninteger power. Examples
include power series generation. With the AD538, only one or
two external resistors are required to set ANY desired power,
over the range of 0.2 to 5. Raising the basic quantity V
power greater than one requires that the gain of the AD538’s log
ratio subtractor be increased, via an external resistor between
pins A and D. Similarly, a voltage divider that attenuates the log
ratio output between points B and C will program the power to
a value less than one.
Figure 15. Basic Configurations and Transfer Functions
for the AD538
REV. C
V
V
V
V
Z
Y
Z
Y
2
10
2
10
B
B
3
3
V
V
REF
REF
R
C
B
12
V
V
Y
Y
C
(
(
V
12
V
V
IN
V
V
REF
REF
A
Z
Z
18
15
15
)
R
)
V
V
m
m
X
C
X
R
20k
A
D
ABSOLUTE VALUE SECTION
17
8
8
2
3
7
+V
20k
1
S
OPTIONAL
–V
R
V
V
IN4148
S
4
B
O
O
20k
8
R
R
R
= R
A
B
C
AD OP-07
OR AD611
(V
TO –V
6
= 196
C
=
OS
5k
M
M –1
1
TAP
IN4148
SCALE FACTOR
200
–1
V
S
OS
)
1/2
1/3
1/4
1/5
POWERS
m
2
3
4
5
ROOTS
m
10k
V
OUT
R
196
97.6
64.9
48.7
Figure 16. Square Root Circuit
100
100
150
162
R
A
100
TRIM
B
1k
1k
+2V
Z
/V
R
100
49.9
49.9
40.2
X
C
+10V
+15V
–15V
to a
+2V
V
V
I
B
O
Z
Z
I
1
2
3
4
5
6
7
8
9
–9–
25k
OUTPUT
*
25k
RATIO MATCH 1% METAL FILM
RESISTORS FOR BEST ACCURACY
SQUARE ROOT OPERATION
The explicit square root circuit of Figure 16 illustrates a precise
method for performing a real-time square root computation. For
added flexibility and accuracy, this circuit has a scale factor
adjustment.
The actual square rooting operation is performed in this circuit
by raising the quantity V
resistor divider network consisting of resistors R
maximum linearity, the two resistors should be 1% (or better)
ratio-matched metal film types.
One volt scaling is achieved by dividing-down the 2 V reference
and applying approximately 1 V to both the V
In this circuit, the V
0.95 V, so that the V
age will be within 3 mV
to 1 mV input range (80 dB). For a decreased input dynamic
range of 10 mV to 10 V (60 dB) the error is even less; here the
output will be within 2 mV
bandwidth of the AD538 square root circuit is approximately
280 kHz with a 1 V p-p sine wave with a +2 V dc offset.
This basic circuit may also be used to compute the cube, fourth
or fifth roots of an input waveform. All that is required for a
given root is that the correct ratio of resistors, R
selected such that their sum is between 150
The optional absolute value circuit shown preceding the AD538
allows the use of bipolar input voltages. Only one op amp is
required for the absolute value function because the I
the AD538 functions as a summing junction. If it is necessary to
preserve the sign of the input voltage, the polarity of the op amp
output may be sensed and used after the computation to switch
the sign bit of a D.V.M. chip.
5% scale factor trim. Using this trim scheme, the output volt-
REFERENCE
INTERNAL
VOLTAGE
V
100
OUT
ANTILOG
RATIO
LOG
= 1V
AD538
LOG
V
1V
IN
100
X
Y
input is intentionally set low, to about
input can be adjusted high, permitting a
Z
25k
/ V
25k
0.2% of the ideal value over a 10 V
X
to the one-half power via the
18
17
16
15
14
13
12
11
10
0.2% of the ideal value. The
A
D
I
V
SIGNAL
GND
PWR
GND
C
I
V
X
Y
X
Y
IN4148
D1
100
100
R
R
B
C
Y
*
*
and 200 .
and V
B
C
and R
and R
AD538
Z
X
input of
inputs.
B
C
, be
. For